1 files changed, 11 insertions, 5 deletions
diff --git a/src/basic_uart.rs b/src/basic_uart.rs
index d7a11be..e5b91f3 100644
--- a/src/basic_uart.rs
+++ b/src/basic_uart.rs
@@ -14,7 +14,7 @@ use std::time::Duration;
 use nix::fcntl::fcntl;
 use nix::fcntl::{FcntlArg, OFlag};
 use trve::consts::{Addr, Byte};
-use trve::exceptions::MemoryExceptionType;
+use trve::exceptions::{MemoryException, MemoryExceptionType};
 use trve::mem::MemDeviceInterface;
 
 /// byte 0: rx/tx
@@ -78,20 +78,26 @@ impl BasicUart {
 }
 
 impl MemDeviceInterface for BasicUart {
-    fn write_byte(&self, addr: Addr, value: Byte) -> Result<(), MemoryExceptionType> {
+    fn write_byte(&self, addr: Addr, value: Byte) -> Result<(), MemoryException> {
         match addr {
             0 => {
                 self.write(value);
                 Ok(())
             }
-            _ => Err(MemoryExceptionType::AccessFault),
+            _ => Err(MemoryException {
+                type_: MemoryExceptionType::AccessFault,
+                addr,
+            }),
         }
     }
-    fn read_byte(&self, addr: Addr) -> Result<Byte, MemoryExceptionType> {
+    fn read_byte(&self, addr: Addr) -> Result<Byte, MemoryException> {
         match addr {
             0 => Ok(self.read()),
             1 => Ok(1 | (self.can_read() as u8) << 1),
-            _ => Err(MemoryExceptionType::AccessFault),
+            _ => Err(MemoryException {
+                type_: MemoryExceptionType::AccessFault,
+                addr,
+            }),
         }
     }
 }