index
:
trve.git
main
Taitep's RISC-V Emulator
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
core.rs
Age
Commit message (
Collapse
)
Author
2025-12-27
Fix some warnings
taitep
2025-12-27
Implement a GDB stub and fix another huge issue in S-type immediate decoding
taitep
2025-12-26
Make macros for R/I-type operations and use them to implement basically ↵
taitep
every single one i think
2025-12-26
(BIG CHANGE) memory handling has changed, MMIO is now a 2 level page table, ↵
taitep
misaligned access supported, addresses not internally split to page and offset immediately, all load/store instructions implemented. Might still have bugs
2025-12-24
Small refactor in exception handling in core.rs
taitep
2025-12-24
EXCEPTION SYSTEM (initial version - may change later)
taitep
2025-12-23
Comment out the unused 'Pause' instruction result
taitep
2025-12-23
Improve error messaging
taitep
2025-12-22
Improve the debug messages when invalid instructions are found (again)
taitep
2025-12-22
Improve the debug messages when invalid instructions are found
taitep
2025-12-22
Fix page offset miscalculation in instruction fetch
taitep
2025-12-22
WHY WAS I USING S-TYPE IMMEDIATE IN LD (also add some more debugging info on ↵
taitep
an exception)
2025-12-21
Make a dedicated function for advancing the PC by one instruction
taitep
2025-12-21
(BIG CHANGE) Switch instruction identification/execution to use a plain ↵
taitep
match tree, should improve performance by quite a bit
2025-12-01
Add license/copyright notices to top of each source file (where applicable)
taitep
2025-10-10
some debugging stuff and SECOND OPCODE!
taitep
2025-10-07
Make sure unsupported/illegal instructions are caught
taitep
2025-10-07
Make fields and register access functions of Core accessible to the rest of ↵
taitep
the emulator
2025-10-04
I guess its a working execution loop?
taitep
2025-10-03
Swap out execution status for instructions returning an InstructionResult
taitep
2025-09-27
base core state & instruction decoder
taitep