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path: root/src/core.rs
AgeCommit message (Collapse)Author
2025-12-27Add exception values (what will go in mtval/stval)taitep
2025-12-27Relicense to BSD 2-Clause to align better with the RISC-V communitytaitep
2025-12-27Fix some warningstaitep
2025-12-27Implement a GDB stub and fix another huge issue in S-type immediate decodingtaitep
2025-12-26Make macros for R/I-type operations and use them to implement basically ↵taitep
every single one i think
2025-12-26(BIG CHANGE) memory handling has changed, MMIO is now a 2 level page table, ↵taitep
misaligned access supported, addresses not internally split to page and offset immediately, all load/store instructions implemented. Might still have bugs
2025-12-24Small refactor in exception handling in core.rstaitep
2025-12-24EXCEPTION SYSTEM (initial version - may change later)taitep
2025-12-23Comment out the unused 'Pause' instruction resulttaitep
2025-12-23Improve error messagingtaitep
2025-12-22Improve the debug messages when invalid instructions are found (again)taitep
2025-12-22Improve the debug messages when invalid instructions are foundtaitep
2025-12-22Fix page offset miscalculation in instruction fetchtaitep
2025-12-22WHY WAS I USING S-TYPE IMMEDIATE IN LD (also add some more debugging info on ↵taitep
an exception)
2025-12-21Make a dedicated function for advancing the PC by one instructiontaitep
2025-12-21(BIG CHANGE) Switch instruction identification/execution to use a plain ↵taitep
match tree, should improve performance by quite a bit
2025-12-01Add license/copyright notices to top of each source file (where applicable)taitep
2025-10-10some debugging stuff and SECOND OPCODE!taitep
2025-10-07Make sure unsupported/illegal instructions are caughttaitep
2025-10-07Make fields and register access functions of Core accessible to the rest of ↵taitep
the emulator
2025-10-04I guess its a working execution loop?taitep
2025-10-03Swap out execution status for instructions returning an InstructionResulttaitep
2025-09-27base core state & instruction decodertaitep