| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2025-12-22 | Fix page offset miscalculation in instruction fetch | taitep | |
| 2025-12-22 | WHY WAS I USING S-TYPE IMMEDIATE IN LD (also add some more debugging info on ↵ | taitep | |
| an exception) | |||
| 2025-12-21 | Make a dedicated function for advancing the PC by one instruction | taitep | |
| 2025-12-21 | (BIG CHANGE) Switch instruction identification/execution to use a plain ↵ | taitep | |
| match tree, should improve performance by quite a bit | |||
| 2025-12-01 | Add license/copyright notices to top of each source file (where applicable) | taitep | |
| 2025-10-10 | some debugging stuff and SECOND OPCODE! | taitep | |
| 2025-10-07 | Make sure unsupported/illegal instructions are caught | taitep | |
| 2025-10-07 | Make fields and register access functions of Core accessible to the rest of ↵ | taitep | |
| the emulator | |||
| 2025-10-04 | I guess its a working execution loop? | taitep | |
| 2025-10-03 | Swap out execution status for instructions returning an InstructionResult | taitep | |
| 2025-09-27 | base core state & instruction decoder | taitep | |
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index : trve.git | |
| Taitep's RISC-V Emulator |
| summaryrefslogtreecommitdiff |