| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2025-10-07 | Make sure unsupported/illegal instructions are caught | taitep | |
| 2025-10-07 | Make fields and register access functions of Core accessible to the rest of ↵ | taitep | |
| the emulator | |||
| 2025-10-04 | I guess its a working execution loop? | taitep | |
| 2025-10-03 | Swap out execution status for instructions returning an InstructionResult | taitep | |
| 2025-09-27 | base core state & instruction decoder | taitep | |
 |
index : trve.git | |
| Taitep's RISC-V Emulator |
| summaryrefslogtreecommitdiff |