index
:
trve.git
main
Taitep's RISC-V Emulator
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
mem.rs
Age
Commit message (
Collapse
)
Author
2025-12-27
Add checks to make sure that ram has a size that is a multiple of 8
taitep
2025-12-27
Relicense to BSD 2-Clause to align better with the RISC-V community
taitep
2025-12-26
(BIG CHANGE) memory handling has changed, MMIO is now a 2 level page table, ↵
taitep
misaligned access supported, addresses not internally split to page and offset immediately, all load/store instructions implemented. Might still have bugs
2025-12-24
Add a default implementation for the memory device interface that just ↵
taitep
returns access faults
2025-12-24
EXCEPTION SYSTEM (initial version - may change later)
taitep
2025-12-01
Add license/copyright notices to top of each source file (where applicable)
taitep
2025-10-09
Make fields of DeviceEntry public
taitep
2025-10-09
Make some constants and type aliases public
taitep
2025-10-07
Make fields of MemConfig public to allow creating one
taitep
2025-09-28
Allow identification of the type of memory (ram or mmio) backing a specific page
taitep
2025-09-27
actually no NOW the memory interface is "done"
taitep
2025-09-27
Initial stuff and memory implementation
taitep
