| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2025-09-27 | base core state & instruction decoder | taitep | |
| 2025-09-27 | actually no NOW the memory interface is "done" | taitep | |
| 2025-09-27 | Initial stuff and memory implementation | taitep | |
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index : trve.git | |
| Taitep's RISC-V Emulator |
| summaryrefslogtreecommitdiff |