From 34034dd5db07f71b0854de0f2bbb18e39aa3db69 Mon Sep 17 00:00:00 2001
From: taitep <taitep@taitep.se>
Date: Fri, 26 Dec 2025 18:14:32 +0100
Subject: Make macros for R/I-type operations and use them to implement
 basically every single one i think

---
 src/instructions.rs | 54 ++++++++++++++++++++++++++++++++++++++++-------------
 1 file changed, 41 insertions(+), 13 deletions(-)

(limited to 'src/instructions.rs')

diff --git a/src/instructions.rs b/src/instructions.rs
index c7af5ec..2942995 100644
--- a/src/instructions.rs
+++ b/src/instructions.rs
@@ -4,6 +4,9 @@
 // This file is part of TRVE (https://gitea.taitep.se/taitep/trve)
 // See LICENSE file in the project root for full license text.
 
+#[macro_use]
+mod macros;
+
 mod rvi;
 
 use crate::{
@@ -14,35 +17,60 @@ use crate::{
 
 pub(crate) fn find_and_exec(instr: Instruction, core: &mut Core) -> Result<(), ExceptionType> {
     match instr.opcode_noncompressed() {
-        0b01100 => match (instr.funct7(), instr.funct3()) {
+        0b01100 => match (instr.funct3(), instr.funct7()) {
             // OP
-            (0b0000000, 0b000) => rvi::add(core, instr),
-            (0b0100000, 0b000) => rvi::sub(core, instr),
-            (0b0000000, 0b111) => rvi::and(core, instr),
-            (0b0000000, 0b110) => rvi::or(core, instr),
+            (0b000, 0b0000000) => rvi::add(core, instr),
+            (0b000, 0b0100000) => rvi::sub(core, instr),
+            (0b010, 0b0000000) => rvi::slt(core, instr),
+            (0b011, 0b0000000) => rvi::sltu(core, instr),
+            (0b001, 0b0000000) => rvi::sll(core, instr),
+            (0b101, 0b0000000) => rvi::srl(core, instr),
+            (0b101, 0b0100000) => rvi::sra(core, instr),
+            (0b111, 0b0000000) => rvi::and(core, instr),
+            (0b100, 0b0000000) => rvi::xor(core, instr),
+            (0b110, 0b0000000) => rvi::or(core, instr),
+            _ => Err(IllegalInstruction),
+        },
+        0b01110 => match (instr.funct3(), instr.funct7()) {
+            // OP_32
+            (0b000, 0b0000000) => rvi::addw(core, instr),
+            (0b000, 0b0100000) => rvi::subw(core, instr),
+            (0b001, 0b0000000) => rvi::sllw(core, instr),
+            (0b101, 0b0000000) => rvi::srlw(core, instr),
+            (0b101, 0b0100000) => rvi::sraw(core, instr),
             _ => Err(IllegalInstruction),
         },
         0b00100 => match instr.funct3() {
             // OP_IMM
             0b000 => rvi::addi(core, instr),
-            0b001 => {
-                if instr.funct6() == 0 {
-                    rvi::slli(core, instr)
-                } else {
-                    Err(IllegalInstruction)
-                }
-            }
+            0b010 => rvi::slti(core, instr),
+            0b011 => rvi::sltiu(core, instr),
+            0b001 => match instr.funct6() {
+                0 => rvi::slli(core, instr),
+                _ => Err(IllegalInstruction),
+            },
             0b101 => match instr.funct6() {
-                // immediate right-shift
                 0b000000 => rvi::srli(core, instr),
+                0b010000 => rvi::srai(core, instr),
                 _ => Err(IllegalInstruction),
             },
+            0b100 => rvi::xori(core, instr),
+            0b110 => rvi::ori(core, instr),
             0b111 => rvi::andi(core, instr),
             _ => Err(IllegalInstruction),
         },
         0b00110 => match instr.funct3() {
             // OP_IMM_32
             0b000 => rvi::addiw(core, instr),
+            0b001 => match instr.funct7() {
+                0 => rvi::slliw(core, instr),
+                _ => Err(IllegalInstruction),
+            },
+            0b101 => match instr.funct7() {
+                0b0000000 => rvi::srliw(core, instr),
+                0b0100000 => rvi::sraiw(core, instr),
+                _ => Err(IllegalInstruction),
+            },
             _ => Err(IllegalInstruction),
         },
         0b01000 => match instr.funct3() {
-- 
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