From 5a383956c9ee27d50452aa237a9f34b7f75e8f7c Mon Sep 17 00:00:00 2001 From: taitep Date: Tue, 30 Dec 2025 20:18:23 +0100 Subject: Improve exception dumps and general debug info, make the emulator capable of running the riscv ISA tests, and perform some general fixes i found while making it pass the tests for RV64I --- src/instructions.rs | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'src/instructions.rs') diff --git a/src/instructions.rs b/src/instructions.rs index 90f2e28..2a224b3 100644 --- a/src/instructions.rs +++ b/src/instructions.rs @@ -131,6 +131,7 @@ pub(crate) fn find_and_exec(instr: Instruction, core: &mut Core) -> Result<(), E // FENCE is just implemented as a SeqCst fence always here // I dont yet care about the potential performance issue this may bring std::sync::atomic::fence(std::sync::atomic::Ordering::SeqCst); + core.advance_pc(); Ok(()) } _ => illegal(instr), @@ -142,7 +143,15 @@ pub(crate) fn find_and_exec(instr: Instruction, core: &mut Core) -> Result<(), E Err(ExceptionType::EnvironmentCallFromMMode.with_no_value()) } (0b000, 0b000000000001, 0, 0) => Err(ExceptionType::Breakpoint.with_no_value()), - _ => illegal(instr), + _ => { + // Temporarily allowing unrecognized instructions here to be able to run + // the official ISA tests, which perform CSR operations but work just fine + // without them + eprintln!("Unrecognized instruction within SYSTEM opcode"); + dbg!(instr); + core.advance_pc(); + Ok(()) + } }, _ => illegal(instr), } -- cgit v1.2.3