From 390a2b322828c10e135022822984826cf108bade Mon Sep 17 00:00:00 2001 From: taitep Date: Sun, 21 Dec 2025 15:56:50 +0100 Subject: Implement LB and LBU --- src/instructions/rvi.rs | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'src/instructions/rvi.rs') diff --git a/src/instructions/rvi.rs b/src/instructions/rvi.rs index 89d142b..98fcb07 100644 --- a/src/instructions/rvi.rs +++ b/src/instructions/rvi.rs @@ -69,6 +69,40 @@ pub fn sb(core: &mut Core, instr: Instruction) -> InstructionResult { } } +pub fn lb(core: &mut Core, instr: Instruction) -> InstructionResult { + let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i()); + + let page = (addr / 4096) as PageNum; + let offset = (addr & (4096 as Addr - 1)) as u16; + + match core.mem.read_byte(page, offset) { + Ok(x) => { + let x = x as i8 as i64 as DWord; + core.reg_write(instr.rd(), x); + core.pc = core.pc.wrapping_add(4); + InstructionResult::Normal + } + Err(_) => InstructionResult::Exception(()), + } +} + +pub fn lbu(core: &mut Core, instr: Instruction) -> InstructionResult { + let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i()); + + let page = (addr / 4096) as PageNum; + let offset = (addr & (4096 as Addr - 1)) as u16; + + match core.mem.read_byte(page, offset) { + Ok(x) => { + let x = x as DWord; + core.reg_write(instr.rd(), x); + core.pc = core.pc.wrapping_add(4); + InstructionResult::Normal + } + Err(_) => InstructionResult::Exception(()), + } +} + pub fn lui(core: &mut Core, instr: Instruction) -> InstructionResult { core.reg_write(instr.rd(), instr.imm_u()); core.pc = core.pc.wrapping_add(4); -- cgit v1.2.3