From c05ba60c3c6ebe89a3db666c316929e0d0d2fdfa Mon Sep 17 00:00:00 2001
From: taitep <taitep@taitep.se>
Date: Sun, 21 Dec 2025 16:29:28 +0100
Subject: Implement ANDI and BEQ

---
 src/instructions/rvi.rs | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

(limited to 'src/instructions/rvi.rs')

diff --git a/src/instructions/rvi.rs b/src/instructions/rvi.rs
index a212b8d..3aadc10 100644
--- a/src/instructions/rvi.rs
+++ b/src/instructions/rvi.rs
@@ -32,6 +32,14 @@ pub fn addiw(core: &mut Core, instr: Instruction) -> InstructionResult {
     InstructionResult::Normal
 }
 
+pub fn andi(core: &mut Core, instr: Instruction) -> InstructionResult {
+    core.reg_write(instr.rd(), core.reg_read(instr.rs1()) & instr.imm_i());
+
+    core.advance_pc();
+
+    InstructionResult::Normal
+}
+
 // TODO: Support misaligned memory access
 pub fn sd(core: &mut Core, instr: Instruction) -> InstructionResult {
     let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());
@@ -115,6 +123,16 @@ pub fn jal(core: &mut Core, instr: Instruction) -> InstructionResult {
     InstructionResult::Normal
 }
 
+pub fn beq(core: &mut Core, instr: Instruction) -> InstructionResult {
+    if core.reg_read(instr.rs1()) == core.reg_read(instr.rs2()) {
+        core.pc = core.pc.wrapping_add(instr.imm_b());
+    } else {
+        core.advance_pc();
+    }
+
+    InstructionResult::Normal
+}
+
 pub fn slli(core: &mut Core, instr: Instruction) -> InstructionResult {
     core.reg_write(instr.rd(), core.reg_read(instr.rs1()) << instr.imm_shamt());
 
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