From d0d3775b888b6cf1e7d240d3426db4175c200b48 Mon Sep 17 00:00:00 2001
From: taitep <taitep@taitep.se>
Date: Mon, 22 Dec 2025 19:29:31 +0100
Subject: Implement OR

---
 src/instructions/rvi.rs | 9 +++++++++
 1 file changed, 9 insertions(+)

(limited to 'src/instructions')

diff --git a/src/instructions/rvi.rs b/src/instructions/rvi.rs
index 395fe8e..69670d0 100644
--- a/src/instructions/rvi.rs
+++ b/src/instructions/rvi.rs
@@ -52,6 +52,15 @@ pub fn andi(core: &mut Core, instr: Instruction) -> InstructionResult {
     InstructionResult::Normal
 }
 
+pub fn or(core: &mut Core, instr: Instruction) -> InstructionResult {
+    core.reg_write(
+        instr.rd(),
+        core.reg_read(instr.rs1()) | core.reg_read(instr.rs2()),
+    );
+    core.advance_pc();
+    InstructionResult::Normal
+}
+
 pub fn slli(core: &mut Core, instr: Instruction) -> InstructionResult {
     core.reg_write(instr.rd(), core.reg_read(instr.rs1()) << instr.imm_shamt());
     core.advance_pc();
-- 
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