From 5a383956c9ee27d50452aa237a9f34b7f75e8f7c Mon Sep 17 00:00:00 2001 From: taitep Date: Tue, 30 Dec 2025 20:18:23 +0100 Subject: Improve exception dumps and general debug info, make the emulator capable of running the riscv ISA tests, and perform some general fixes i found while making it pass the tests for RV64I --- src/mem.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mem.rs') diff --git a/src/mem.rs b/src/mem.rs index e3cbe82..a3b087c 100644 --- a/src/mem.rs +++ b/src/mem.rs @@ -263,8 +263,8 @@ impl Ram { if !addr.is_multiple_of(8) { let high_word_addr = addr.wrapping_add(4); - let low_word = self.read_byte(addr)?; - let high_word = self.read_byte(high_word_addr)?; + let low_word = self.read_word(addr)?; + let high_word = self.read_word(high_word_addr)?; return Ok((low_word as u64) | (high_word as u64) << 32); } -- cgit v1.2.3