// Copyright (c) 2025 taitep
// SPDX-License-Identifier: MIT
//
// This file is part of TRVE (https://gitea.taitep.se/taitep/trve)
// See LICENSE file in the project root for full license text.

use crate::{
    core::{Core, InstructionResult},
    decode::Instruction,
};

mod mem;

pub use mem::*;

pub fn add(core: &mut Core, instr: Instruction) -> InstructionResult {
    core.reg_write(
        instr.rd(),
        core.reg_read(instr.rs1())
            .wrapping_add(core.reg_read(instr.rs2())),
    );
    core.advance_pc();
    InstructionResult::Normal
}

pub fn sub(core: &mut Core, instr: Instruction) -> InstructionResult {
    core.reg_write(
        instr.rd(),
        core.reg_read(instr.rs1())
            .wrapping_sub(core.reg_read(instr.rs2())),
    );
    core.advance_pc();
    InstructionResult::Normal
}

pub fn addi(core: &mut Core, instr: Instruction) -> InstructionResult {
    core.reg_write(
        instr.rd(),
        core.reg_read(instr.rs1()).wrapping_add(instr.imm_i()),
    );
    core.advance_pc();
    InstructionResult::Normal
}

pub fn addiw(core: &mut Core, instr: Instruction) -> InstructionResult {
    let res = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i()) as i32;
    core.reg_write(instr.rd(), res as i64 as u64);
    core.advance_pc();
    InstructionResult::Normal
}

pub fn and(core: &mut Core, instr: Instruction) -> InstructionResult {
    core.reg_write(
        instr.rd(),
        core.reg_read(instr.rs1()) & core.reg_read(instr.rs2()),
    );
    core.advance_pc();
    InstructionResult::Normal
}

pub fn andi(core: &mut Core, instr: Instruction) -> InstructionResult {
    core.reg_write(instr.rd(), core.reg_read(instr.rs1()) & instr.imm_i());
    core.advance_pc();
    InstructionResult::Normal
}

pub fn or(core: &mut Core, instr: Instruction) -> InstructionResult {
    core.reg_write(
        instr.rd(),
        core.reg_read(instr.rs1()) | core.reg_read(instr.rs2()),
    );
    core.advance_pc();
    InstructionResult::Normal
}

pub fn slli(core: &mut Core, instr: Instruction) -> InstructionResult {
    core.reg_write(instr.rd(), core.reg_read(instr.rs1()) << instr.imm_shamt());
    core.advance_pc();
    InstructionResult::Normal
}

pub fn lui(core: &mut Core, instr: Instruction) -> InstructionResult {
    core.reg_write(instr.rd(), instr.imm_u());
    core.advance_pc();
    InstructionResult::Normal
}

pub fn auipc(core: &mut Core, instr: Instruction) -> InstructionResult {
    core.reg_write(instr.rd(), core.pc.wrapping_add(instr.imm_u()));
    core.advance_pc();
    InstructionResult::Normal
}

pub fn jal(core: &mut Core, instr: Instruction) -> InstructionResult {
    core.reg_write(instr.rd(), core.pc.wrapping_add(4));
    core.pc = core.pc.wrapping_add(instr.imm_j());
    InstructionResult::Normal
}

pub fn jalr(core: &mut Core, instr: Instruction) -> InstructionResult {
    core.reg_write(instr.rd(), core.pc.wrapping_add(4));
    core.pc = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
    InstructionResult::Normal
}

pub fn beq(core: &mut Core, instr: Instruction) -> InstructionResult {
    if core.reg_read(instr.rs1()) == core.reg_read(instr.rs2()) {
        core.pc = core.pc.wrapping_add(instr.imm_b());
    } else {
        core.advance_pc();
    }

    InstructionResult::Normal
}

pub fn bne(core: &mut Core, instr: Instruction) -> InstructionResult {
    if core.reg_read(instr.rs1()) != core.reg_read(instr.rs2()) {
        core.pc = core.pc.wrapping_add(instr.imm_b());
    } else {
        core.advance_pc();
    }

    InstructionResult::Normal
}

pub fn bgeu(core: &mut Core, instr: Instruction) -> InstructionResult {
    if core.reg_read(instr.rs1()) >= core.reg_read(instr.rs2()) {
        core.pc = core.pc.wrapping_add(instr.imm_b());
    } else {
        core.advance_pc();
    }

    InstructionResult::Normal
}

pub fn bltu(core: &mut Core, instr: Instruction) -> InstructionResult {
    if core.reg_read(instr.rs1()) < core.reg_read(instr.rs2()) {
        core.pc = core.pc.wrapping_add(instr.imm_b());
    } else {
        core.advance_pc();
    }

    InstructionResult::Normal
}