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authortaitep <taitep@taitep.se>2025-10-07 20:16:27 +0200
committertaitep <taitep@taitep.se>2025-10-07 20:16:27 +0200
commit361b36fbd1ba4a710abbc866da1c641545a6d53f (patch)
treefc15d6dabe54100a299118a95d089a9f50965e7d
parentdbd022f9c9e7409e74059224431f57de6bec7238 (diff)
Make sure unsupported/illegal instructions are caught
-rw-r--r--src/core.rs5
-rw-r--r--src/decode.rs2
2 files changed, 6 insertions, 1 deletions
diff --git a/src/core.rs b/src/core.rs
index 8f6aaa7..9e82521 100644
--- a/src/core.rs
+++ b/src/core.rs
@@ -47,6 +47,8 @@ impl Core {
}
};
+ assert_eq!(instr & 3, 3, "Compressed instructions not supported");
+
let instr = Instruction(instr);
let runner = find_runner(instr);
@@ -65,6 +67,9 @@ impl Core {
break;
}
}
+ } else {
+ eprintln!("Invalid Instruction");
+ break;
}
}
}
diff --git a/src/decode.rs b/src/decode.rs
index 409aedb..5e19ab9 100644
--- a/src/decode.rs
+++ b/src/decode.rs
@@ -12,7 +12,7 @@ impl Instruction {
/// Returns the opcode of the instruction, with the last 2 bits stripped away, as they are always 0b11 in a non-compressed instruction
pub fn opcode_noncompressed(&self) -> u8 {
- debug_assert_eq!(self.0 & 0b11, 0b11);
+ debug_assert_eq!(self.0 & 0b11, 0b11, "Compressed (or invalid) opcode");
(self.0 >> 2 & 0x1f) as u8
}