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authortaitep <taitep@taitep.se>2025-12-21 13:03:18 +0100
committertaitep <taitep@taitep.se>2025-12-21 13:03:18 +0100
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treea00ef2330c242ed5f3d658fc336fc6671157c794 /README.md
parente8da0fc3966950d5a35c7e17ae4baa6293c454ce (diff)
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# trve
-RISC-V Emulator. The goal is to support at least RV64GC and be able to run Linux, potentially more. No plans for RV32I or RV32/64E. \ No newline at end of file
+taitep's RISC-V Emulator.
+The goal is to support at least RV64GC and be able to run Linux,
+potentially more. No plans for RV32I or RV32/64E.
+
+## Current Use
+Currently, the emulator is nowhere near complete,
+its not even at rv64i, but it does work for a subset of it.
+
+The emulator will load a raw binary image from the file `./img` into RAM,
+which starts at 0x80000000 and is currently 1MiB,
+and start execution at the start of the image/ram.
+
+There is also a debug out page starting at `0x00000000`-`0x00001000`.
+Anything written to it will be logged out in hex.
+
+Currently there is no input, altho i might get around to making
+an early UART kinda soon.