Add a basic UART (very much temporary, its performance is most likely horrible

1 files changed, 154 insertions, 0 deletions

diff --git a/src/basic_uart.rs b/src/basic_uart.rs
new file mode 100644
index 0000000..04230a2
--- /dev/null
+++ b/src/basic_uart.rs
@@ -0,0 +1,154 @@
+use std::collections::VecDeque;
+use std::io::{Read, Write, stdin, stdout};
+use std::sync::{Arc, Mutex};
+use std::thread;
+use std::time::Duration;
+
+use trve::consts::{Byte, DWord, HWord, Word};
+use trve::mem::{MemAccessFault, MemDeviceInterface, PageNum};
+
+/// byte 0: rx/tx
+/// byte 1: status (------rt, r=rxready, t=txready)/none
+pub struct BasicUart {
+    buffers: Mutex<UartBuffers>,
+}
+
+struct UartBuffers {
+    rx: VecDeque<u8>,
+    tx: VecDeque<u8>,
+}
+
+impl BasicUart {
+    pub fn new() -> Self {
+        BasicUart {
+            buffers: Mutex::new(UartBuffers {
+                rx: VecDeque::new(),
+                tx: VecDeque::new(),
+            }),
+        }
+    }
+
+    pub fn spawn_poller(self, poll_interval: Duration) -> Arc<Self> {
+        let shared = Arc::new(self);
+
+        let uart_clone = shared.clone();
+
+        thread::spawn(move || {
+            loop {
+                uart_clone.poll();
+                thread::sleep(poll_interval);
+            }
+        });
+
+        shared
+    }
+
+    fn write(&self, byte: u8) {
+        let mut bufs = self.buffers.lock().unwrap();
+        bufs.tx.push_back(byte);
+    }
+
+    fn read(&self) -> u8 {
+        let mut bufs = self.buffers.lock().unwrap();
+        bufs.rx.pop_front().unwrap_or(0)
+    }
+
+    fn can_read(&self) -> bool {
+        let bufs = self.buffers.lock().unwrap();
+        !bufs.rx.is_empty()
+    }
+
+    pub fn poll(&self) {
+        let mut bufs = self.buffers.lock().unwrap();
+
+        while let Some(byte) = bufs.tx.pop_front() {
+            print!("{}", byte as char);
+        }
+        stdout().flush().unwrap();
+
+        let mut buffer = [0u8; 1];
+        if let Ok(n) = stdin().read(&mut buffer) {
+            if n > 0 {
+                bufs.rx.push_back(buffer[0]);
+            }
+        }
+    }
+}
+
+impl MemDeviceInterface for BasicUart {
+    fn write_dword(
+        &self,
+        _page: PageNum,
+        _offset: u16,
+        _value: DWord,
+    ) -> Result<(), MemAccessFault> {
+        Err(MemAccessFault)
+    }
+
+    fn write_word(&self, _page: PageNum, _offset: u16, _value: Word) -> Result<(), MemAccessFault> {
+        Err(MemAccessFault)
+    }
+
+    fn write_hword(
+        &self,
+        _page: PageNum,
+        _offset: u16,
+        _value: HWord,
+    ) -> Result<(), MemAccessFault> {
+        Err(MemAccessFault)
+    }
+
+    fn write_byte(&self, page: PageNum, offset: u16, value: Byte) -> Result<(), MemAccessFault> {
+        if page > 0 {
+            return Err(MemAccessFault);
+        }
+
+        match offset {
+            0 => {
+                self.write(value);
+                Ok(())
+            }
+            _ => Err(MemAccessFault),
+        }
+    }
+
+    fn read_dword(&self, _page: PageNum, _offset: u16) -> Result<DWord, MemAccessFault> {
+        Err(MemAccessFault)
+    }
+
+    fn read_word(&self, _page: PageNum, _offset: u16) -> Result<Word, MemAccessFault> {
+        Err(MemAccessFault)
+    }
+
+    fn read_hword(&self, _page: PageNum, _offset: u16) -> Result<HWord, MemAccessFault> {
+        Err(MemAccessFault)
+    }
+
+    fn read_byte(&self, page: PageNum, offset: u16) -> Result<Byte, MemAccessFault> {
+        if page > 0 {
+            return Err(MemAccessFault);
+        }
+
+        match offset {
+            0 => Ok(self.read()),
+            1 => Ok(1 | (self.can_read() as u8) << 1),
+            _ => Err(MemAccessFault),
+        }
+    }
+
+    fn get_atomic_word(
+        &self,
+        _page: PageNum,
+        _offset: u16,
+    ) -> Result<&std::sync::atomic::AtomicU32, MemAccessFault> {
+        Err(MemAccessFault)
+    }
+
+    fn get_atomic_dword(
+        &self,
+        _page: PageNum,
+        _offset: u16,
+    ) -> Result<&std::sync::atomic::AtomicU64, MemAccessFault> {
+        Err(MemAccessFault)
+    }
+}