diff options
| author | taitep <taitep@taitep.se> | 2025-12-24 13:56:41 +0100 |
|---|---|---|
| committer | taitep <taitep@taitep.se> | 2025-12-24 13:56:41 +0100 |
| commit | 09d90643726d2a86952473e27b6e5d64543e41a0 (patch) | |
| tree | 52d0ebf404675e1ae359dd77af406131a0623111 /src/basic_uart.rs | |
| parent | 3f789442c0be7d0222209d98dde21efcff7602d0 (diff) | |
EXCEPTION SYSTEM (initial version - may change later)
Diffstat (limited to 'src/basic_uart.rs')
| -rw-r--r-- | src/basic_uart.rs | 47 |
1 files changed, 24 insertions, 23 deletions
diff --git a/src/basic_uart.rs b/src/basic_uart.rs index 3380515..ec687e3 100644 --- a/src/basic_uart.rs +++ b/src/basic_uart.rs @@ -14,7 +14,8 @@ use std::time::Duration; use nix::fcntl::fcntl; use nix::fcntl::{FcntlArg, OFlag}; use trve::consts::{Byte, DWord, HWord, Word}; -use trve::mem::{MemAccessFault, MemDeviceInterface, PageNum}; +use trve::exceptions::ExceptionType; +use trve::mem::{MemDeviceInterface, PageNum}; /// byte 0: rx/tx /// byte 1: status (------rt, r=rxready, t=txready)/none @@ -82,12 +83,12 @@ impl MemDeviceInterface for BasicUart { _page: PageNum, _offset: u16, _value: DWord, - ) -> Result<(), MemAccessFault> { - Err(MemAccessFault) + ) -> Result<(), ExceptionType> { + Err(ExceptionType::StoreAmoAccessFault) } - fn write_word(&self, _page: PageNum, _offset: u16, _value: Word) -> Result<(), MemAccessFault> { - Err(MemAccessFault) + fn write_word(&self, _page: PageNum, _offset: u16, _value: Word) -> Result<(), ExceptionType> { + Err(ExceptionType::StoreAmoAccessFault) } fn write_hword( @@ -95,13 +96,13 @@ impl MemDeviceInterface for BasicUart { _page: PageNum, _offset: u16, _value: HWord, - ) -> Result<(), MemAccessFault> { - Err(MemAccessFault) + ) -> Result<(), ExceptionType> { + Err(ExceptionType::StoreAmoAccessFault) } - fn write_byte(&self, page: PageNum, offset: u16, value: Byte) -> Result<(), MemAccessFault> { + fn write_byte(&self, page: PageNum, offset: u16, value: Byte) -> Result<(), ExceptionType> { if page > 0 { - return Err(MemAccessFault); + return Err(ExceptionType::StoreAmoAccessFault); } match offset { @@ -109,31 +110,31 @@ impl MemDeviceInterface for BasicUart { self.write(value); Ok(()) } - _ => Err(MemAccessFault), + _ => Err(ExceptionType::StoreAmoAccessFault), } } - fn read_dword(&self, _page: PageNum, _offset: u16) -> Result<DWord, MemAccessFault> { - Err(MemAccessFault) + fn read_dword(&self, _page: PageNum, _offset: u16) -> Result<DWord, ExceptionType> { + Err(ExceptionType::LoadAccessFault) } - fn read_word(&self, _page: PageNum, _offset: u16) -> Result<Word, MemAccessFault> { - Err(MemAccessFault) + fn read_word(&self, _page: PageNum, _offset: u16) -> Result<Word, ExceptionType> { + Err(ExceptionType::LoadAccessFault) } - fn read_hword(&self, _page: PageNum, _offset: u16) -> Result<HWord, MemAccessFault> { - Err(MemAccessFault) + fn read_hword(&self, _page: PageNum, _offset: u16) -> Result<HWord, ExceptionType> { + Err(ExceptionType::LoadAccessFault) } - fn read_byte(&self, page: PageNum, offset: u16) -> Result<Byte, MemAccessFault> { + fn read_byte(&self, page: PageNum, offset: u16) -> Result<Byte, ExceptionType> { if page > 0 { - return Err(MemAccessFault); + return Err(ExceptionType::LoadAccessFault); } match offset { 0 => Ok(self.read()), 1 => Ok(1 | (self.can_read() as u8) << 1), - _ => Err(MemAccessFault), + _ => Err(ExceptionType::LoadAccessFault), } } @@ -141,15 +142,15 @@ impl MemDeviceInterface for BasicUart { &self, _page: PageNum, _offset: u16, - ) -> Result<&std::sync::atomic::AtomicU32, MemAccessFault> { - Err(MemAccessFault) + ) -> Result<&std::sync::atomic::AtomicU32, ExceptionType> { + Err(ExceptionType::StoreAmoAccessFault) } fn get_atomic_dword( &self, _page: PageNum, _offset: u16, - ) -> Result<&std::sync::atomic::AtomicU64, MemAccessFault> { - Err(MemAccessFault) + ) -> Result<&std::sync::atomic::AtomicU64, ExceptionType> { + Err(ExceptionType::StoreAmoAccessFault) } } |
