Improve exception dumps and general debug info, make the emulator capable of running the riscv ISA tests, and perform some general fixes i found while making it pass the tests for RV64I

1 files changed, 2 insertions, 1 deletions

diff --git a/src/core.rs b/src/core.rs
index 07df2f5..64a6a25 100644
--- a/src/core.rs
+++ b/src/core.rs
@@ -164,7 +164,7 @@ impl Core {
         let instr = Instruction(instr);
 
         if let Err(e) = find_and_exec(instr, self) {
-            eprintln!("instr: {:08x}", instr.0);
+            dbg!(instr);
             return Err(e);
         }
 
@@ -174,6 +174,7 @@ impl Core {
     fn throw_exception(&mut self, exception: Exception) {
         eprintln!("Exception: {exception:?}");
         dbg!(self.pc, self.x_regs);
+        dbg!(self.x_regs[10]);
     }
 
     pub fn reset(&mut self, pc: u64) {