Replace custom UART with a sifive uart subset

2 files changed, 253 insertions, 0 deletions

diff --git a/src/devices/serial.rs b/src/devices/serial.rs
new file mode 100644
index 0000000..7e90748
--- /dev/null
+++ b/src/devices/serial.rs
@@ -0,0 +1,140 @@
+// Copyright (c) 2026 taitep
+// SPDX-License-Identifier: BSD-2-Clause
+//
+// This file is part of TRVE (https://gitea.taitep.se/taitep/trve)
+// See LICENSE file in the project root for full license text.
+
+use std::{
+    io::{Read, Write},
+    sync::{Arc, Mutex},
+    time::Duration,
+};
+
+mod fifo;
+use fifo::UartFifo;
+
+use crate::{exceptions::MemoryExceptionType, mem::MemDeviceInterface};
+
+pub struct SifiveUart {
+    rx: Mutex<(UartFifo<2048>, bool)>,
+    tx: Mutex<(UartFifo<2048>, bool)>,
+}
+
+impl SifiveUart {
+    pub fn new_arc() -> Arc<Self> {
+        Arc::new(Self {
+            rx: Mutex::new((UartFifo::default(), false)),
+            tx: Mutex::new((UartFifo::default(), false)),
+        })
+    }
+
+    pub fn spawn_io_thread<R: Read + Send + 'static, T: Write + Send + Sync + 'static>(
+        self: Arc<Self>,
+        mut rx_backend: R,
+        mut tx_backend: T,
+        interval: Duration,
+    ) {
+        std::thread::spawn(move || {
+            loop {
+                {
+                    // Read data
+                    let mut rx_guard = self.rx.lock().expect("could not lock uart RX half");
+                    let (rx_buf, rx_en) = &mut *rx_guard;
+
+                    if *rx_en {
+                        let _ = rx_buf.read_from(&mut rx_backend);
+                    }
+                }
+                {
+                    // Write data
+                    let mut tx_guard = self.tx.lock().expect("could not lock uart RX half");
+                    let (tx_buf, tx_en) = &mut *tx_guard;
+
+                    if *tx_en {
+                        let _ = tx_buf.write_to(&mut tx_backend);
+                        let _ = tx_backend.flush();
+                    }
+                }
+
+                std::thread::sleep(interval);
+            }
+        });
+    }
+}
+
+impl MemDeviceInterface for SifiveUart {
+    fn write_word(&self, addr: u64, value: u32) -> Result<(), MemoryExceptionType> {
+        // dbg!(addr, value);
+        match addr {
+            0x00 => {
+                // TXDATA
+                let (ref mut tx_buf, _) = *self.tx.lock().expect("could not lock uart TX half");
+                tx_buf.push_single_byte(value as u8);
+                Ok(())
+            }
+            0x08 => {
+                // TXCTRL
+                let (_, ref mut tx_en) = *self.tx.lock().expect("could not lock uart TX half");
+                *tx_en = value & 1 != 0;
+                Ok(())
+            }
+            0x04 => Ok(()), // RXDATA
+            0x0c => {
+                // RXCTRL
+                let (_, ref mut rx_en) = *self.rx.lock().expect("could not lock uart RX half");
+                *rx_en = value & 1 != 0;
+                Ok(())
+            }
+            0x10 => Ok(()), // IE
+            0x14 => Ok(()), // IP
+            0x18 => Ok(()), // DIV
+            _ => {
+                if addr < 0x1c {
+                    Err(MemoryExceptionType::AddressMisaligned)
+                } else {
+                    Err(MemoryExceptionType::AccessFault)
+                }
+            }
+        }
+    }
+
+    fn read_word(&self, addr: u64) -> Result<u32, MemoryExceptionType> {
+        // dbg!(addr);
+        match addr {
+            0x00 => {
+                // TXDATA
+                let (ref tx_buf, _) = *self.tx.lock().expect("could not lock uart TX half");
+                Ok(if tx_buf.is_full() { 0x80000000 } else { 0 })
+            }
+            0x08 => {
+                // TXCTRL
+                let (_, tx_en) = *self.tx.lock().expect("could not lock uart TX half");
+                Ok(if tx_en { 1 } else { 0 })
+            }
+            0x04 => {
+                // RXDATA
+                let (ref mut rx_buf, _) = *self.rx.lock().expect("could not lock uart RX half");
+                Ok(match rx_buf.pop_single_byte() {
+                    None => 0x80000000,
+                    Some(b) => b as u32,
+                })
+            }
+            0x0c => {
+                // RXCTRL
+                let (_, rx_en) = *self.rx.lock().expect("could not lock uart RX half");
+                Ok(if rx_en { 1 } else { 0 })
+            }
+            0x10 => Ok(0), // IE
+            0x14 => Ok(0), // IP
+            0x18 => Ok(1), // DIV
+
+            _ => {
+                if addr < 0x1c {
+                    Err(MemoryExceptionType::AddressMisaligned)
+                } else {
+                    Err(MemoryExceptionType::AccessFault)
+                }
+            }
+        }
+    }
+}
diff --git a/src/devices/serial/fifo.rs b/src/devices/serial/fifo.rs
new file mode 100644
index 0000000..dbf4659
--- /dev/null
+++ b/src/devices/serial/fifo.rs
@@ -0,0 +1,113 @@
+// Copyright (c) 2026 taitep
+// SPDX-License-Identifier: BSD-2-Clause
+//
+// This file is part of TRVE (https://gitea.taitep.se/taitep/trve)
+// See LICENSE file in the project root for full license text.
+
+use std::io::{self, Read, Write};
+
+pub struct UartFifo<const CAP: usize> {
+    buf: [u8; CAP],
+    head: usize,
+    tail: usize,
+    len: usize,
+}
+
+impl<const CAP: usize> UartFifo<CAP> {
+    pub fn pop_single_byte(&mut self) -> Option<u8> {
+        if self.is_empty() {
+            return None;
+        }
+
+        let value = self.buf[self.tail];
+        self.advance_read(1);
+        Some(value)
+    }
+
+    pub fn push_single_byte(&mut self, value: u8) -> bool {
+        if self.is_full() {
+            return false;
+        }
+
+        self.buf[self.head] = value;
+        self.advance_write(1);
+        true
+    }
+
+    pub fn is_empty(&self) -> bool {
+        self.len == 0
+    }
+
+    pub fn is_full(&self) -> bool {
+        self.len == CAP
+    }
+
+    fn write_slice(&mut self) -> &mut [u8] {
+        if self.is_full() {
+            return &mut [];
+        }
+
+        if self.head >= self.tail {
+            &mut self.buf[self.head..]
+        } else {
+            &mut self.buf[self.head..self.tail]
+        }
+    }
+
+    fn advance_write(&mut self, n: usize) {
+        debug_assert!(n <= CAP - self.len);
+        self.head = (self.head + n) % CAP;
+        self.len += n;
+    }
+
+    fn read_slice(&self) -> &[u8] {
+        if self.is_empty() {
+            return &[];
+        }
+
+        if self.tail < self.head {
+            &self.buf[self.tail..self.head]
+        } else {
+            &self.buf[self.tail..]
+        }
+    }
+
+    fn advance_read(&mut self, n: usize) {
+        debug_assert!(n <= self.len);
+        self.tail = (self.tail + n) % CAP;
+        self.len -= n;
+    }
+
+    pub fn read_from<R: Read>(&mut self, reader: &mut R) -> io::Result<usize> {
+        let slice = self.write_slice();
+        if slice.is_empty() {
+            return Ok(0);
+        }
+
+        let n = reader.read(slice)?;
+        self.advance_write(n);
+        Ok(n)
+    }
+
+    pub fn write_to<W: Write>(&mut self, writer: &mut W) -> io::Result<usize> {
+        let slice = self.read_slice();
+        if slice.is_empty() {
+            return Ok(0);
+        }
+
+        let n = writer.write(slice)?;
+        self.advance_read(n);
+        Ok(n)
+    }
+}
+
+impl<const SIZE: usize> Default for UartFifo<SIZE> {
+    fn default() -> Self {
+        UartFifo {
+            buf: [0; SIZE],
+            head: 0,
+            tail: 0,
+            len: 0,
+        }
+    }
+}