Make MMIO devices not have control of the address of exceptions

1 files changed, 11 insertions, 11 deletions

diff --git a/src/instructions/rvi/mem.rs b/src/instructions/rvi/mem.rs
index caa18e1..ad08a39 100644
--- a/src/instructions/rvi/mem.rs
+++ b/src/instructions/rvi/mem.rs
@@ -11,7 +11,7 @@ pub fn sd(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
     let value = core.reg_read(instr.rs2());
     core.mem
         .write_dword(addr, value)
-        .map_err(|e| e.to_exception_store())?;
+        .map_err(|e| e.into_exception_store())?;
     core.advance_pc();
     Ok(())
 }
@@ -22,7 +22,7 @@ pub fn ld(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
         instr.rd(),
         core.mem
             .read_dword(addr)
-            .map_err(|e| e.to_exception_load())?,
+            .map_err(|e| e.into_exception_load())?,
     );
     core.advance_pc();
     Ok(())
@@ -33,7 +33,7 @@ pub fn sw(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
     let value = core.reg_read(instr.rs2()) as u32;
     core.mem
         .write_word(addr, value)
-        .map_err(|e| e.to_exception_store())?;
+        .map_err(|e| e.into_exception_store())?;
     core.advance_pc();
     Ok(())
 }
@@ -44,7 +44,7 @@ pub fn lw(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
         instr.rd(),
         core.mem
             .read_word(addr)
-            .map_err(|e| e.to_exception_load())? as i32 as i64 as u64,
+            .map_err(|e| e.into_exception_load())? as i32 as i64 as u64,
     );
     core.advance_pc();
     Ok(())
@@ -56,7 +56,7 @@ pub fn lwu(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
         instr.rd(),
         core.mem
             .read_word(addr)
-            .map_err(|e| e.to_exception_load())? as u64,
+            .map_err(|e| e.into_exception_load())? as u64,
     );
     core.advance_pc();
     Ok(())
@@ -67,7 +67,7 @@ pub fn sh(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
     let value = core.reg_read(instr.rs2()) as u16;
     core.mem
         .write_hword(addr, value)
-        .map_err(|e| e.to_exception_store())?;
+        .map_err(|e| e.into_exception_store())?;
     core.advance_pc();
     Ok(())
 }
@@ -78,7 +78,7 @@ pub fn lh(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
         instr.rd(),
         core.mem
             .read_hword(addr)
-            .map_err(|e| e.to_exception_load())? as i16 as i64 as u64,
+            .map_err(|e| e.into_exception_load())? as i16 as i64 as u64,
     );
     core.advance_pc();
     Ok(())
@@ -90,7 +90,7 @@ pub fn lhu(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
         instr.rd(),
         core.mem
             .read_hword(addr)
-            .map_err(|e| e.to_exception_load())? as u64,
+            .map_err(|e| e.into_exception_load())? as u64,
     );
     core.advance_pc();
     Ok(())
@@ -101,7 +101,7 @@ pub fn sb(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
     let value = core.reg_read(instr.rs2()) as u8;
     core.mem
         .write_byte(addr, value)
-        .map_err(|e| e.to_exception_store())?;
+        .map_err(|e| e.into_exception_store())?;
     core.advance_pc();
     Ok(())
 }
@@ -112,7 +112,7 @@ pub fn lb(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
         instr.rd(),
         core.mem
             .read_byte(addr)
-            .map_err(|e| e.to_exception_load())? as i8 as i64 as u64,
+            .map_err(|e| e.into_exception_load())? as i8 as i64 as u64,
     );
     core.advance_pc();
     Ok(())
@@ -124,7 +124,7 @@ pub fn lbu(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
         instr.rd(),
         core.mem
             .read_byte(addr)
-            .map_err(|e| e.to_exception_load())? as u64,
+            .map_err(|e| e.into_exception_load())? as u64,
     );
     core.advance_pc();
     Ok(())