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authortaitep <taitep@taitep.se>2025-12-22 22:48:57 +0100
committertaitep <taitep@taitep.se>2025-12-22 22:48:57 +0100
commit0ac363e203c7ea830b095fe353c00ad9cfc0aa3b (patch)
tree0add655bed7f5ba2cdd0e3a641243d8a1da2bc5a /src/instructions/rvi
parent7a22570a0f5a16bcfb10e9af7127ef55124716aa (diff)
Implement LW
Diffstat (limited to 'src/instructions/rvi')
-rw-r--r--src/instructions/rvi/mem.rs20
1 files changed, 20 insertions, 0 deletions
diff --git a/src/instructions/rvi/mem.rs b/src/instructions/rvi/mem.rs
index c57e079..d065e8d 100644
--- a/src/instructions/rvi/mem.rs
+++ b/src/instructions/rvi/mem.rs
@@ -66,6 +66,26 @@ pub fn sw(core: &mut Core, instr: Instruction) -> InstructionResult {
}
}
+pub fn lw(core: &mut Core, instr: Instruction) -> InstructionResult {
+ let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
+
+ if !addr.is_multiple_of(std::mem::size_of::<Word>() as Addr) {
+ return InstructionResult::Exception(());
+ }
+
+ let page = (addr / 4096) as PageNum;
+ let offset = (addr / 4 & ((4096 / 4 as Addr) - 1)) as u16;
+
+ match core.mem.read_word(page, offset) {
+ Ok(x) => {
+ core.reg_write(instr.rd(), x as i32 as i64 as DWord);
+ core.advance_pc();
+ InstructionResult::Normal
+ }
+ Err(_) => InstructionResult::Exception(()),
+ }
+}
+
pub fn lh(core: &mut Core, instr: Instruction) -> InstructionResult {
let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());