Improve exception dumps and general debug info, make the emulator capable of running the riscv ISA tests, and perform some general fixes i found while making it pass the tests for RV64I

1 files changed, 3 insertions, 2 deletions

diff --git a/src/instructions/rvi.rs b/src/instructions/rvi.rs
index 424e9e4..78267ea 100644
--- a/src/instructions/rvi.rs
+++ b/src/instructions/rvi.rs
@@ -32,7 +32,7 @@ instr_op!(srl, srli, |x, shamt| x >> (shamt & 0b111111));
 instr_op!(
     srlw,
     srliw,
-    |x, shamt| (x >> (shamt & 0b11111)) as i32 as i64 as u64
+    |x, shamt| (x as u32 >> (shamt & 0b11111)) as i32 as i64 as u64
 );
 instr_op!(sra, srai, |x, shamt| (x as i64 >> (shamt & 0b111111))
     as u64);
@@ -64,8 +64,9 @@ pub fn jal(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
 }
 
 pub fn jalr(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
+    let target = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i()) & !1;
     core.reg_write(instr.rd(), core.pc.wrapping_add(4));
-    core.pc = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
+    core.pc = target;
     Ok(())
 }