Add exception values (what will go in mtval/stval)

3 files changed, 20 insertions, 20 deletions

diff --git a/src/instructions/macros.rs b/src/instructions/macros.rs
index 98cf63d..c8fa8f1 100644
--- a/src/instructions/macros.rs
+++ b/src/instructions/macros.rs
@@ -7,7 +7,7 @@
 #[macro_export]
 macro_rules! instr_branch {
     ($name:ident, $cond:expr) => {
-        pub fn $name(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
+        pub fn $name(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
             let a = core.reg_read(instr.rs1());
             let b = core.reg_read(instr.rs2());
             if $cond(a, b) {
@@ -30,7 +30,7 @@ macro_rules! instr_branch_signed {
 #[macro_export]
 macro_rules! instr_op_r {
     ($name:ident, $op:expr) => {
-        pub fn $name(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
+        pub fn $name(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
             let a = core.reg_read(instr.rs1());
             let b = core.reg_read(instr.rs2());
             let res = $op(a, b);
@@ -44,7 +44,7 @@ macro_rules! instr_op_r {
 #[macro_export]
 macro_rules! instr_op_i {
     ($name:ident, $op:expr) => {
-        pub fn $name(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
+        pub fn $name(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
             let a = core.reg_read(instr.rs1());
             let b = instr.imm_i();
             let res = $op(a, b);
diff --git a/src/instructions/rvi.rs b/src/instructions/rvi.rs
index 5e2faa4..9f34fb1 100644
--- a/src/instructions/rvi.rs
+++ b/src/instructions/rvi.rs
@@ -4,7 +4,7 @@
 // This file is part of TRVE (https://gitea.taitep.se/taitep/trve)
 // See LICENSE file in the project root for full license text.
 
-use crate::{consts::RegValue, core::Core, decode::Instruction, exceptions::ExceptionType};
+use crate::{consts::RegValue, core::Core, decode::Instruction, exceptions::Exception};
 
 use std::ops::{BitAnd, BitOr, BitXor};
 
@@ -49,25 +49,25 @@ instr_op!(
 instr_op!(sltu, sltiu, |a, b| (a < b) as RegValue);
 instr_op!(slt, slti, |a, b| ((a as i64) < (b as i64)) as RegValue);
 
-pub fn lui(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
+pub fn lui(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
     core.reg_write(instr.rd(), instr.imm_u());
     core.advance_pc();
     Ok(())
 }
 
-pub fn auipc(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
+pub fn auipc(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
     core.reg_write(instr.rd(), core.pc.wrapping_add(instr.imm_u()));
     core.advance_pc();
     Ok(())
 }
 
-pub fn jal(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
+pub fn jal(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
     core.reg_write(instr.rd(), core.pc.wrapping_add(4));
     core.pc = core.pc.wrapping_add(instr.imm_j());
     Ok(())
 }
 
-pub fn jalr(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
+pub fn jalr(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
     core.reg_write(instr.rd(), core.pc.wrapping_add(4));
     core.pc = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
     Ok(())
diff --git a/src/instructions/rvi/mem.rs b/src/instructions/rvi/mem.rs
index 73e4179..071fa79 100644
--- a/src/instructions/rvi/mem.rs
+++ b/src/instructions/rvi/mem.rs
@@ -7,11 +7,11 @@
 use crate::{
     consts::{Byte, DWord, HWord, Word},
     core::Core,
-    exceptions::ExceptionType,
+    exceptions::Exception,
     instructions::Instruction,
 };
 
-pub fn sd(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
+pub fn sd(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
     let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());
     let value = core.reg_read(instr.rs2());
     core.mem
@@ -21,7 +21,7 @@ pub fn sd(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
     Ok(())
 }
 
-pub fn ld(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
+pub fn ld(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
     let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
     core.reg_write(
         instr.rd(),
@@ -33,7 +33,7 @@ pub fn ld(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
     Ok(())
 }
 
-pub fn sw(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
+pub fn sw(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
     let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());
     let value = core.reg_read(instr.rs2()) as Word;
     core.mem
@@ -43,7 +43,7 @@ pub fn sw(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
     Ok(())
 }
 
-pub fn lw(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
+pub fn lw(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
     let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
     core.reg_write(
         instr.rd(),
@@ -55,7 +55,7 @@ pub fn lw(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
     Ok(())
 }
 
-pub fn lwu(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
+pub fn lwu(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
     let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
     core.reg_write(
         instr.rd(),
@@ -67,7 +67,7 @@ pub fn lwu(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
     Ok(())
 }
 
-pub fn sh(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
+pub fn sh(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
     let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());
     let value = core.reg_read(instr.rs2()) as HWord;
     core.mem
@@ -77,7 +77,7 @@ pub fn sh(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
     Ok(())
 }
 
-pub fn lh(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
+pub fn lh(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
     let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
     core.reg_write(
         instr.rd(),
@@ -89,7 +89,7 @@ pub fn lh(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
     Ok(())
 }
 
-pub fn lhu(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
+pub fn lhu(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
     let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
     core.reg_write(
         instr.rd(),
@@ -101,7 +101,7 @@ pub fn lhu(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
     Ok(())
 }
 
-pub fn sb(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
+pub fn sb(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
     let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());
     let value = core.reg_read(instr.rs2()) as Byte;
     core.mem
@@ -111,7 +111,7 @@ pub fn sb(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
     Ok(())
 }
 
-pub fn lb(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
+pub fn lb(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
     let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
     core.reg_write(
         instr.rd(),
@@ -123,7 +123,7 @@ pub fn lb(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
     Ok(())
 }
 
-pub fn lbu(core: &mut Core, instr: Instruction) -> Result<(), ExceptionType> {
+pub fn lbu(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
     let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
     core.reg_write(
         instr.rd(),