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authortaitep <taitep@taitep.se>2025-12-21 15:27:39 +0100
committertaitep <taitep@taitep.se>2025-12-21 15:27:39 +0100
commit0457530e0c91ad64065e3a63fad41a25ff312b36 (patch)
tree102d6a38b8cb8fc111b1764e0a374ec92e0f80a2 /src/main.rs
parenteec40b069ad6cf8e91c358bf37b5518e4b0623ff (diff)
Add a basic UART (very much temporary, its performance is most likely horrible
Diffstat (limited to 'src/main.rs')
-rw-r--r--src/main.rs25
1 files changed, 20 insertions, 5 deletions
diff --git a/src/main.rs b/src/main.rs
index ef3e772..cdaa6eb 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -9,6 +9,7 @@ use std::{
fs::File,
io::{self, Read},
sync::Arc,
+ time::Duration,
};
use trve::{
@@ -17,6 +18,8 @@ use trve::{
mem::{DeviceEntry, MemAccessFault, MemConfig, MemDeviceInterface, PageNum, Ram},
};
+use crate::basic_uart::BasicUart;
+
fn read_file_to_buffer(path: &str, buffer: &mut [u8]) -> io::Result<usize> {
let mut file = File::open(path)?;
let mut total_read = 0;
@@ -42,14 +45,24 @@ fn main() -> Result<(), Box<dyn Error>> {
let buf = ram.buf_mut();
read_file_to_buffer("./img", buf)?;
+ let uart = BasicUart::new();
+ let uart = uart.spawn_poller(Duration::from_millis(10));
+
let mem_cfg = MemConfig {
ram: Arc::new(ram),
ram_start: 0x8000_0000 / 4096,
- devices: Box::new([DeviceEntry {
- base: 0,
- size: 1,
- interface: Arc::new(DbgOut),
- }]),
+ devices: Box::new([
+ DeviceEntry {
+ base: 0,
+ size: 1,
+ interface: Arc::new(DbgOut),
+ },
+ DeviceEntry {
+ base: 1,
+ size: 1,
+ interface: uart,
+ },
+ ]),
};
let mut core = Core::new(mem_cfg);
@@ -59,6 +72,8 @@ fn main() -> Result<(), Box<dyn Error>> {
Ok(())
}
+mod basic_uart;
+
struct DbgOut;
impl MemDeviceInterface for DbgOut {