Replace custom UART with a sifive uart subset

1 files changed, 13 insertions, 7 deletions

diff --git a/src/main.rs b/src/main.rs
index 7be2d20..50d5de0 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -4,12 +4,14 @@
 // This file is part of TRVE (https://gitea.taitep.se/taitep/trve)
 // See LICENSE file in the project root for full license text.
 
-use std::{path::PathBuf, sync::Arc, time::Duration};
+use std::{io, os::fd::AsFd, path::PathBuf, sync::Arc, time::Duration};
 
 use clap::Parser;
 
+use nix::fcntl::{FcntlArg, OFlag, fcntl};
 use trve::{
     core::Core,
+    devices,
     exceptions::MemoryExceptionType,
     gdb,
     mem::{MemConfig, MemDeviceInterface, MmioRoot, Ram},
@@ -17,8 +19,6 @@ use trve::{
 
 use anyhow::Result;
 
-use crate::basic_uart::BasicUart;
-
 mod execload;
 
 /// Taitep's RISC-V Emulator
@@ -42,8 +42,16 @@ fn main() -> Result<()> {
     let mut mmio_root = MmioRoot::default();
     mmio_root.insert(0, Arc::new(DbgOut));
 
-    let uart = BasicUart::new();
-    let uart = uart.spawn_poller(Duration::from_millis(10));
+    if let Err(e) = fcntl(io::stdin().as_fd(), FcntlArg::F_SETFL(OFlag::O_NONBLOCK)) {
+        eprintln!("Could not make stdout nonblocking, skipping. Error: {e}");
+    }
+
+    let uart = devices::serial::SifiveUart::new_arc();
+    uart.clone().spawn_io_thread(
+        std::io::stdin(),
+        std::io::stdout(),
+        Duration::from_millis(10),
+    );
     mmio_root.insert(0x10000, uart);
 
     let mem_cfg = MemConfig {
@@ -67,8 +75,6 @@ fn main() -> Result<()> {
     Ok(())
 }
 
-mod basic_uart;
-
 struct DbgOut;
 
 impl MemDeviceInterface for DbgOut {