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authortaitep <taitep@taitep.se>2025-10-07 20:12:09 +0200
committertaitep <taitep@taitep.se>2025-10-07 20:12:09 +0200
commitdbd022f9c9e7409e74059224431f57de6bec7238 (patch)
tree0bd770a5ca8c0206148ba46b38f64b8884ed13c1 /src
parent908be749acd2c03d4a7366cfdbb81242b615cf8c (diff)
Make fields and register access functions of Core accessible to the rest of the emulator
Diffstat (limited to 'src')
-rw-r--r--src/core.rs10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/core.rs b/src/core.rs
index 5a0cbe5..8f6aaa7 100644
--- a/src/core.rs
+++ b/src/core.rs
@@ -15,9 +15,9 @@ pub(crate) enum InstructionResult {
}
pub struct Core {
- x_regs: [RegValue; 32],
- pc: Addr,
- mem: MemConfig,
+ pub(crate) x_regs: [RegValue; 32],
+ pub(crate) pc: Addr,
+ pub(crate) mem: MemConfig,
}
impl Core {
@@ -73,11 +73,11 @@ impl Core {
self.pc = pc;
}
- fn reg_read(&self, id: RegId) -> RegValue {
+ pub(crate) fn reg_read(&self, id: RegId) -> RegValue {
self.x_regs[id as usize]
}
- fn reg_write(&mut self, id: RegId, value: RegValue) {
+ pub(crate) fn reg_write(&mut self, id: RegId, value: RegValue) {
if id == 0 {
return;
}