3 files changed, 56 insertions, 0 deletions
diff --git a/src/instructions/gen_tools.rs b/src/instructions/gen_tools.rs
new file mode 100644
index 0000000..ad9ad62
--- /dev/null
+++ b/src/instructions/gen_tools.rs
@@ -0,0 +1,22 @@
+use std::hint::unreachable_unchecked;
+
+use crate::instructions::{OpcodeHandler, Splitter};
+
+pub fn insert_funct3_splitter(splitter: &mut Option<Splitter>) -> &mut [OpcodeHandler; 8] {
+    match splitter {
+        Some(Splitter::Funct3Splitter(s)) => s.as_mut(),
+        Some(_) => panic!("Unexpected splitter variant"),
+        None => {
+            *splitter = Some(Splitter::Funct3Splitter(Box::new(std::array::from_fn(
+                |_i| OpcodeHandler {
+                    handler: None,
+                    splitter: None,
+                },
+            ))));
+            match splitter {
+                Some(Splitter::Funct3Splitter(s)) => s.as_mut(),
+                _ => unsafe { unreachable_unchecked() },
+            }
+        }
+    }
+}
diff --git a/src/instructions/opcodes.rs b/src/instructions/opcodes.rs
new file mode 100644
index 0000000..33f824d
--- /dev/null
+++ b/src/instructions/opcodes.rs
@@ -0,0 +1,6 @@
+//! Includes opcodes, funct3 values, and match/mask values.
+//! Opcodes (unless compressed) have the last 2 bits stripped off as they are always 1s for non-compressed instructions.
+
+pub(super) const OP_IMM: u8 = 0b00100;
+
+pub(super) const FUNCT3_ADDI: u8 = 0x0;
diff --git a/src/instructions/rvi.rs b/src/instructions/rvi.rs
new file mode 100644
index 0000000..8e7dade
--- /dev/null
+++ b/src/instructions/rvi.rs
@@ -0,0 +1,28 @@
+use crate::{
+    core::{Core, InstructionResult},
+    decode::Instruction,
+    instructions::{
+        OpcodeHandler,
+        gen_tools::insert_funct3_splitter,
+        opcodes::{FUNCT3_ADDI, OP_IMM},
+    },
+};
+
+pub(super) fn add_instrs(list: &mut [OpcodeHandler; 32]) {
+    let funct3_split_op_imm = insert_funct3_splitter(&mut list[OP_IMM as usize].splitter);
+    funct3_split_op_imm[FUNCT3_ADDI as usize].handler =
+        Some(super::InstructionHandler { runner: addi });
+}
+
+fn addi(core: &mut Core, instr: Instruction) -> InstructionResult {
+    eprintln!("Running ADDI");
+
+    core.reg_write(
+        instr.rd(),
+        core.reg_read(instr.rs1()).wrapping_add(instr.imm_i()),
+    );
+
+    core.pc = core.pc.wrapping_add(4);
+
+    InstructionResult::Normal
+}