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-rw-r--r--src/instructions.rs1
-rw-r--r--src/instructions/rvi.rs14
2 files changed, 11 insertions, 4 deletions
diff --git a/src/instructions.rs b/src/instructions.rs
index eead29f..bfedaee 100644
--- a/src/instructions.rs
+++ b/src/instructions.rs
@@ -29,6 +29,7 @@ pub(crate) fn find_and_exec(instr: Instruction, core: &mut Core) -> Option<Instr
_ => None,
},
0b01101 => Some(rvi::lui(core, instr)),
+ 0b11011 => Some(rvi::jal(core, instr)),
_ => None,
}
}
diff --git a/src/instructions/rvi.rs b/src/instructions/rvi.rs
index feff85b..2d342df 100644
--- a/src/instructions/rvi.rs
+++ b/src/instructions/rvi.rs
@@ -11,7 +11,7 @@ use crate::{
mem::PageNum,
};
-pub(super) fn addi(core: &mut Core, instr: Instruction) -> InstructionResult {
+pub fn addi(core: &mut Core, instr: Instruction) -> InstructionResult {
core.reg_write(
instr.rd(),
core.reg_read(instr.rs1()).wrapping_add(instr.imm_i()),
@@ -22,7 +22,7 @@ pub(super) fn addi(core: &mut Core, instr: Instruction) -> InstructionResult {
InstructionResult::Normal
}
-pub(super) fn addiw(core: &mut Core, instr: Instruction) -> InstructionResult {
+pub fn addiw(core: &mut Core, instr: Instruction) -> InstructionResult {
let res = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i()) as i32;
core.reg_write(instr.rd(), res as i64 as u64);
@@ -33,7 +33,7 @@ pub(super) fn addiw(core: &mut Core, instr: Instruction) -> InstructionResult {
}
// TODO: Support misaligned memory access
-pub(super) fn sd(core: &mut Core, instr: Instruction) -> InstructionResult {
+pub fn sd(core: &mut Core, instr: Instruction) -> InstructionResult {
let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());
if !addr.is_multiple_of(std::mem::size_of::<DWord>() as Addr) {
@@ -53,8 +53,14 @@ pub(super) fn sd(core: &mut Core, instr: Instruction) -> InstructionResult {
}
}
-pub(super) fn lui(core: &mut Core, instr: Instruction) -> InstructionResult {
+pub fn lui(core: &mut Core, instr: Instruction) -> InstructionResult {
core.reg_write(instr.rd(), instr.imm_u());
core.pc = core.pc.wrapping_add(4);
InstructionResult::Normal
}
+
+pub fn jal(core: &mut Core, instr: Instruction) -> InstructionResult {
+ core.reg_write(instr.rd(), core.pc);
+ core.pc = core.pc.wrapping_add(instr.imm_j());
+ InstructionResult::Normal
+}