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Taitep's RISC-V Emulator
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2025-10-10
some debugging stuff and SECOND OPCODE!
taitep
2025-10-09
Make fields of DeviceEntry public
taitep
2025-10-09
Make some constants and type aliases public
taitep
2025-10-07
FIRST INSTRUCTION WORKING
taitep
2025-10-07
Make sure unsupported/illegal instructions are caught
taitep
2025-10-07
Make fields and register access functions of Core accessible to the rest of ↵
taitep
the emulator
2025-10-07
Make fields of MemConfig public to allow creating one
taitep
2025-10-04
I guess its a working execution loop?
taitep
2025-10-03
Swap out execution status for instructions returning an InstructionResult
taitep
2025-09-30
Initial instruction execution code i guess
taitep
2025-09-28
Allow identification of the type of memory (ram or mmio) backing a specific page
taitep
2025-09-27
base core state & instruction decoder
taitep
2025-09-27
actually no NOW the memory interface is "done"
taitep
2025-09-27
Initial stuff and memory implementation
taitep
2025-09-27
Initial Readme
taitep
2025-09-06
Initial commit
taitep
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