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Taitep's RISC-V Emulator
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instructions.rs
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Author
2025-12-22
Implement AND and improve formatting and ordering in rvi.rs
taitep
2025-12-22
Implement ADD
taitep
2025-12-21
Implement LD and BNE
taitep
2025-12-21
Implement JALR, fix JAL, change how some stuff in instructions.rs is expressed
taitep
2025-12-21
Implement AUIPC
taitep
2025-12-21
Implement ANDI and BEQ
taitep
2025-12-21
Implement LB and LBU
taitep
2025-12-21
Implement SB
taitep
2025-12-21
Implement SLLI and fix sign extension of immediates for I-type and S-type ins...
taitep
2025-12-21
Add JAL and change some of the formatting on previous instructions to be cleaner
taitep
2025-12-21
(BIG CHANGE) Switch instruction identification/execution to use a plain match...
taitep
2025-12-01
Add license/copyright notices to top of each source file (where applicable)
taitep
2025-10-07
FIRST INSTRUCTION WORKING
taitep
2025-10-04
I guess its a working execution loop?
taitep
2025-10-03
Swap out execution status for instructions returning an InstructionResult
taitep
2025-09-30
Initial instruction execution code i guess
taitep