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# trve
taitep's RISC-V Emulator.
The goal is to support at least RV64GC and be able to run Linux,
potentially more. No plans for RV32I or RV32/64E.
## Current Use
Currently, the emulator is nowhere near complete,
its not even at rv64i, but it does work for a subset of it.
The emulator will load a raw binary image from a file specified as a CLI argument into RAM,
which starts at 0x80000000 and is currently 16MiB,
and start execution at the start of the image/ram.
There is also a debug out page starting at `0x00000000`-`0x00001000`.
Anything written to it will be logged out in hex.
There is also a UART at `0x00001000`-`0x00002000`, the interface is quite simple:
- byte `0`: Data. When written, writes out the character
When read, reads a character from the buffer, or 0 if empty.
- byte `1`: Status. Read-only. Least significant bit is `TX_READY` and indicates whether
the UART is ready to be written to. Currently always 1.
Next least significant is `RX_READY`, indicates whether the read buffer
has any data to read.
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