1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
|
// Copyright (c) 2026 taitep
// SPDX-License-Identifier: BSD-2-Clause
//
// This file is part of TRVE (https://gitea.taitep.se/taitep/trve)
// See LICENSE file in the project root for full license text.
use std::{
io::{Read, Write},
sync::{Arc, Mutex},
time::Duration,
};
mod fifo;
use fifo::UartFifo;
use crate::{exceptions::MemoryExceptionType, mem::MemDeviceInterface};
pub struct SifiveUart {
rx: Mutex<(UartFifo<2048>, bool)>,
tx: Mutex<(UartFifo<2048>, bool)>,
}
impl SifiveUart {
pub fn new_arc() -> Arc<Self> {
Arc::new(Self {
rx: Mutex::new((UartFifo::default(), false)),
tx: Mutex::new((UartFifo::default(), false)),
})
}
pub fn spawn_io_thread<R: Read + Send + 'static, T: Write + Send + Sync + 'static>(
self: Arc<Self>,
mut rx_backend: R,
mut tx_backend: T,
interval: Duration,
) {
std::thread::spawn(move || {
loop {
{
// Read data
let mut rx_guard = self.rx.lock().expect("could not lock uart RX half");
let (rx_buf, rx_en) = &mut *rx_guard;
if *rx_en {
let _ = rx_buf.read_from(&mut rx_backend);
}
}
{
// Write data
let mut tx_guard = self.tx.lock().expect("could not lock uart RX half");
let (tx_buf, tx_en) = &mut *tx_guard;
if *tx_en {
let _ = tx_buf.write_to(&mut tx_backend);
let _ = tx_backend.flush();
}
}
std::thread::sleep(interval);
}
});
}
}
impl MemDeviceInterface for SifiveUart {
fn write_word(&self, addr: u64, value: u32) -> Result<(), MemoryExceptionType> {
// dbg!(addr, value);
match addr {
0x00 => {
// TXDATA
let (ref mut tx_buf, _) = *self.tx.lock().expect("could not lock uart TX half");
tx_buf.push_single_byte(value as u8);
Ok(())
}
0x08 => {
// TXCTRL
let (_, ref mut tx_en) = *self.tx.lock().expect("could not lock uart TX half");
*tx_en = value & 1 != 0;
Ok(())
}
0x04 => Ok(()), // RXDATA
0x0c => {
// RXCTRL
let (_, ref mut rx_en) = *self.rx.lock().expect("could not lock uart RX half");
*rx_en = value & 1 != 0;
Ok(())
}
0x10 => Ok(()), // IE
0x14 => Ok(()), // IP
0x18 => Ok(()), // DIV
_ => {
if addr < 0x1c {
Err(MemoryExceptionType::AddressMisaligned)
} else {
Err(MemoryExceptionType::AccessFault)
}
}
}
}
fn read_word(&self, addr: u64) -> Result<u32, MemoryExceptionType> {
// dbg!(addr);
match addr {
0x00 => {
// TXDATA
let (ref tx_buf, _) = *self.tx.lock().expect("could not lock uart TX half");
Ok(if tx_buf.is_full() { 0x80000000 } else { 0 })
}
0x08 => {
// TXCTRL
let (_, tx_en) = *self.tx.lock().expect("could not lock uart TX half");
Ok(if tx_en { 1 } else { 0 })
}
0x04 => {
// RXDATA
let (ref mut rx_buf, _) = *self.rx.lock().expect("could not lock uart RX half");
Ok(match rx_buf.pop_single_byte() {
None => 0x80000000,
Some(b) => b as u32,
})
}
0x0c => {
// RXCTRL
let (_, rx_en) = *self.rx.lock().expect("could not lock uart RX half");
Ok(if rx_en { 1 } else { 0 })
}
0x10 => Ok(0), // IE
0x14 => Ok(0), // IP
0x18 => Ok(1), // DIV
_ => {
if addr < 0x1c {
Err(MemoryExceptionType::AddressMisaligned)
} else {
Err(MemoryExceptionType::AccessFault)
}
}
}
}
}
|
