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// Copyright (c) 2025 taitep
// SPDX-License-Identifier: MIT
//
// This file is part of TRVE (https://gitea.taitep.se/taitep/trve)
// See LICENSE file in the project root for full license text.
use crate::{
consts::{Addr, DWord},
core::{Core, InstructionResult},
decode::Instruction,
instructions::{
OpcodeHandler,
gen_tools::insert_funct3_splitter,
opcodes::{OP_IMM, OP_IMM_32, STORE},
},
mem::PageNum,
};
pub(super) fn add_instrs(list: &mut [OpcodeHandler; 32]) {
let funct3_splitter = insert_funct3_splitter(&mut list[OP_IMM as usize].splitter); // OP-IMM
funct3_splitter[0b000].handler = Some(super::InstructionHandler { runner: addi }); // ADDI
let funct3_splitter = insert_funct3_splitter(&mut list[OP_IMM_32 as usize].splitter); // OP-IMM-32
funct3_splitter[0b000].handler = Some(super::InstructionHandler { runner: addiw }); //ADDIW
let funct3_splitter = insert_funct3_splitter(&mut list[STORE as usize].splitter); // STORE
funct3_splitter[0b011].handler = Some(super::InstructionHandler { runner: sd }); // SD
list[0b01101].handler = Some(super::InstructionHandler { runner: lui }); //LUI
}
fn addi(core: &mut Core, instr: Instruction) -> InstructionResult {
core.reg_write(
instr.rd(),
core.reg_read(instr.rs1()).wrapping_add(instr.imm_i()),
);
core.pc = core.pc.wrapping_add(4);
InstructionResult::Normal
}
fn addiw(core: &mut Core, instr: Instruction) -> InstructionResult {
let res = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i()) as i32;
core.reg_write(instr.rd(), res as i64 as u64);
core.pc = core.pc.wrapping_add(4);
InstructionResult::Normal
}
// TODO: Support misaligned memory access
fn sd(core: &mut Core, instr: Instruction) -> InstructionResult {
let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s());
if !addr.is_multiple_of(std::mem::size_of::<DWord>() as Addr) {
return InstructionResult::Exception(());
}
let page = (addr / 4096) as PageNum;
let offset = (addr & ((4096 / std::mem::size_of::<DWord>() as Addr) - 1)) as u16;
let value = core.reg_read(instr.rs2());
match core.mem.write_dword(page, offset, value) {
Ok(_) => {
core.pc = core.pc.wrapping_add(4);
InstructionResult::Normal
}
Err(_) => InstructionResult::Exception(()),
}
}
fn lui(core: &mut Core, instr: Instruction) -> InstructionResult {
core.reg_write(instr.rd(), instr.imm_u());
core.pc = core.pc.wrapping_add(4);
InstructionResult::Normal
}
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