summaryrefslogtreecommitdiff
path: root/src/instructions/rvi.rs
diff options
context:
space:
mode:
authortaitep <taitep@taitep.se>2025-12-21 15:56:50 +0100
committertaitep <taitep@taitep.se>2025-12-21 15:56:50 +0100
commit390a2b322828c10e135022822984826cf108bade (patch)
tree0afe43bba9d53441353aff0b1e9838656789ce7a /src/instructions/rvi.rs
parent25ecfca912d9451d567827aceafe405b68b2d256 (diff)
Implement LB and LBU
Diffstat (limited to 'src/instructions/rvi.rs')
-rw-r--r--src/instructions/rvi.rs34
1 files changed, 34 insertions, 0 deletions
diff --git a/src/instructions/rvi.rs b/src/instructions/rvi.rs
index 89d142b..98fcb07 100644
--- a/src/instructions/rvi.rs
+++ b/src/instructions/rvi.rs
@@ -69,6 +69,40 @@ pub fn sb(core: &mut Core, instr: Instruction) -> InstructionResult {
}
}
+pub fn lb(core: &mut Core, instr: Instruction) -> InstructionResult {
+ let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
+
+ let page = (addr / 4096) as PageNum;
+ let offset = (addr & (4096 as Addr - 1)) as u16;
+
+ match core.mem.read_byte(page, offset) {
+ Ok(x) => {
+ let x = x as i8 as i64 as DWord;
+ core.reg_write(instr.rd(), x);
+ core.pc = core.pc.wrapping_add(4);
+ InstructionResult::Normal
+ }
+ Err(_) => InstructionResult::Exception(()),
+ }
+}
+
+pub fn lbu(core: &mut Core, instr: Instruction) -> InstructionResult {
+ let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_i());
+
+ let page = (addr / 4096) as PageNum;
+ let offset = (addr & (4096 as Addr - 1)) as u16;
+
+ match core.mem.read_byte(page, offset) {
+ Ok(x) => {
+ let x = x as DWord;
+ core.reg_write(instr.rd(), x);
+ core.pc = core.pc.wrapping_add(4);
+ InstructionResult::Normal
+ }
+ Err(_) => InstructionResult::Exception(()),
+ }
+}
+
pub fn lui(core: &mut Core, instr: Instruction) -> InstructionResult {
core.reg_write(instr.rd(), instr.imm_u());
core.pc = core.pc.wrapping_add(4);