summaryrefslogtreecommitdiff
path: root/src/instructions
diff options
context:
space:
mode:
authortaitep <taitep@taitep.se>2025-12-22 19:29:31 +0100
committertaitep <taitep@taitep.se>2025-12-22 19:29:31 +0100
commitd0d3775b888b6cf1e7d240d3426db4175c200b48 (patch)
tree263d686efbc5fd7a32ec30206e36634a0108e7a9 /src/instructions
parent1ddda6614a929ea141755d20a09f564d80e63b99 (diff)
Implement OR
Diffstat (limited to 'src/instructions')
-rw-r--r--src/instructions/rvi.rs9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/instructions/rvi.rs b/src/instructions/rvi.rs
index 395fe8e..69670d0 100644
--- a/src/instructions/rvi.rs
+++ b/src/instructions/rvi.rs
@@ -52,6 +52,15 @@ pub fn andi(core: &mut Core, instr: Instruction) -> InstructionResult {
InstructionResult::Normal
}
+pub fn or(core: &mut Core, instr: Instruction) -> InstructionResult {
+ core.reg_write(
+ instr.rd(),
+ core.reg_read(instr.rs1()) | core.reg_read(instr.rs2()),
+ );
+ core.advance_pc();
+ InstructionResult::Normal
+}
+
pub fn slli(core: &mut Core, instr: Instruction) -> InstructionResult {
core.reg_write(instr.rd(), core.reg_read(instr.rs1()) << instr.imm_shamt());
core.advance_pc();