1 files changed, 15 insertions, 19 deletions

diff --git a/src/instructions/rvi.rs b/src/instructions/rvi.rs
index 9f34fb1..424e9e4 100644
--- a/src/instructions/rvi.rs
+++ b/src/instructions/rvi.rs
@@ -4,7 +4,7 @@
 // This file is part of TRVE (https://gitea.taitep.se/taitep/trve)
 // See LICENSE file in the project root for full license text.
 
-use crate::{consts::RegValue, core::Core, decode::Instruction, exceptions::Exception};
+use crate::{core::Core, decode::Instruction, exceptions::Exception};
 
 use std::ops::{BitAnd, BitOr, BitXor};
 
@@ -12,42 +12,38 @@ mod mem;
 
 pub use mem::*;
 
-instr_op!(add, addi, RegValue::wrapping_add);
-instr_op!(
-    addw,
-    addiw,
-    |a, b| RegValue::wrapping_add(a, b) as i32 as i64 as RegValue
-);
-instr_op_r!(sub, RegValue::wrapping_sub);
-instr_op_r!(subw, |a, b| RegValue::wrapping_sub(a, b) as i32 as i64
-    as RegValue);
+instr_op!(add, addi, u64::wrapping_add);
+instr_op!(addw, addiw, |a, b| u64::wrapping_add(a, b) as i32 as i64
+    as u64);
+instr_op_r!(sub, u64::wrapping_sub);
+instr_op_r!(subw, |a, b| u64::wrapping_sub(a, b) as i32 as i64 as u64);
 
-instr_op!(and, andi, RegValue::bitand);
-instr_op!(or, ori, RegValue::bitor);
-instr_op!(xor, xori, RegValue::bitxor);
+instr_op!(and, andi, u64::bitand);
+instr_op!(or, ori, u64::bitor);
+instr_op!(xor, xori, u64::bitxor);
 
 instr_op!(sll, slli, |x, shamt| x << (shamt & 0b111111));
 instr_op!(
     sllw,
     slliw,
-    |x, shamt| (x << (shamt & 0b11111)) as i32 as i64 as RegValue
+    |x, shamt| (x << (shamt & 0b11111)) as i32 as i64 as u64
 );
 instr_op!(srl, srli, |x, shamt| x >> (shamt & 0b111111));
 instr_op!(
     srlw,
     srliw,
-    |x, shamt| (x >> (shamt & 0b11111)) as i32 as i64 as RegValue
+    |x, shamt| (x >> (shamt & 0b11111)) as i32 as i64 as u64
 );
 instr_op!(sra, srai, |x, shamt| (x as i64 >> (shamt & 0b111111))
-    as RegValue);
+    as u64);
 instr_op!(
     sraw,
     sraiw,
-    |x, shamt| (x as i32 >> (shamt & 0b11111)) as i64 as RegValue
+    |x, shamt| (x as i32 >> (shamt & 0b11111)) as i64 as u64
 );
 
-instr_op!(sltu, sltiu, |a, b| (a < b) as RegValue);
-instr_op!(slt, slti, |a, b| ((a as i64) < (b as i64)) as RegValue);
+instr_op!(sltu, sltiu, |a, b| (a < b) as u64);
+instr_op!(slt, slti, |a, b| ((a as i64) < (b as i64)) as u64);
 
 pub fn lui(core: &mut Core, instr: Instruction) -> Result<(), Exception> {
     core.reg_write(instr.rd(), instr.imm_u());