diff options
Diffstat (limited to 'src/instructions')
| -rw-r--r-- | src/instructions/rvi.rs | 34 | ||||
| -rw-r--r-- | src/instructions/rvi/mem.rs | 25 |
2 files changed, 25 insertions, 34 deletions
diff --git a/src/instructions/rvi.rs b/src/instructions/rvi.rs index 9f34fb1..424e9e4 100644 --- a/src/instructions/rvi.rs +++ b/src/instructions/rvi.rs @@ -4,7 +4,7 @@ // This file is part of TRVE (https://gitea.taitep.se/taitep/trve) // See LICENSE file in the project root for full license text. -use crate::{consts::RegValue, core::Core, decode::Instruction, exceptions::Exception}; +use crate::{core::Core, decode::Instruction, exceptions::Exception}; use std::ops::{BitAnd, BitOr, BitXor}; @@ -12,42 +12,38 @@ mod mem; pub use mem::*; -instr_op!(add, addi, RegValue::wrapping_add); -instr_op!( - addw, - addiw, - |a, b| RegValue::wrapping_add(a, b) as i32 as i64 as RegValue -); -instr_op_r!(sub, RegValue::wrapping_sub); -instr_op_r!(subw, |a, b| RegValue::wrapping_sub(a, b) as i32 as i64 - as RegValue); +instr_op!(add, addi, u64::wrapping_add); +instr_op!(addw, addiw, |a, b| u64::wrapping_add(a, b) as i32 as i64 + as u64); +instr_op_r!(sub, u64::wrapping_sub); +instr_op_r!(subw, |a, b| u64::wrapping_sub(a, b) as i32 as i64 as u64); -instr_op!(and, andi, RegValue::bitand); -instr_op!(or, ori, RegValue::bitor); -instr_op!(xor, xori, RegValue::bitxor); +instr_op!(and, andi, u64::bitand); +instr_op!(or, ori, u64::bitor); +instr_op!(xor, xori, u64::bitxor); instr_op!(sll, slli, |x, shamt| x << (shamt & 0b111111)); instr_op!( sllw, slliw, - |x, shamt| (x << (shamt & 0b11111)) as i32 as i64 as RegValue + |x, shamt| (x << (shamt & 0b11111)) as i32 as i64 as u64 ); instr_op!(srl, srli, |x, shamt| x >> (shamt & 0b111111)); instr_op!( srlw, srliw, - |x, shamt| (x >> (shamt & 0b11111)) as i32 as i64 as RegValue + |x, shamt| (x >> (shamt & 0b11111)) as i32 as i64 as u64 ); instr_op!(sra, srai, |x, shamt| (x as i64 >> (shamt & 0b111111)) - as RegValue); + as u64); instr_op!( sraw, sraiw, - |x, shamt| (x as i32 >> (shamt & 0b11111)) as i64 as RegValue + |x, shamt| (x as i32 >> (shamt & 0b11111)) as i64 as u64 ); -instr_op!(sltu, sltiu, |a, b| (a < b) as RegValue); -instr_op!(slt, slti, |a, b| ((a as i64) < (b as i64)) as RegValue); +instr_op!(sltu, sltiu, |a, b| (a < b) as u64); +instr_op!(slt, slti, |a, b| ((a as i64) < (b as i64)) as u64); pub fn lui(core: &mut Core, instr: Instruction) -> Result<(), Exception> { core.reg_write(instr.rd(), instr.imm_u()); diff --git a/src/instructions/rvi/mem.rs b/src/instructions/rvi/mem.rs index 071fa79..caa18e1 100644 --- a/src/instructions/rvi/mem.rs +++ b/src/instructions/rvi/mem.rs @@ -4,12 +4,7 @@ // This file is part of TRVE (https://gitea.taitep.se/taitep/trve) // See LICENSE file in the project root for full license text. -use crate::{ - consts::{Byte, DWord, HWord, Word}, - core::Core, - exceptions::Exception, - instructions::Instruction, -}; +use crate::{core::Core, exceptions::Exception, instructions::Instruction}; pub fn sd(core: &mut Core, instr: Instruction) -> Result<(), Exception> { let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s()); @@ -35,7 +30,7 @@ pub fn ld(core: &mut Core, instr: Instruction) -> Result<(), Exception> { pub fn sw(core: &mut Core, instr: Instruction) -> Result<(), Exception> { let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s()); - let value = core.reg_read(instr.rs2()) as Word; + let value = core.reg_read(instr.rs2()) as u32; core.mem .write_word(addr, value) .map_err(|e| e.to_exception_store())?; @@ -49,7 +44,7 @@ pub fn lw(core: &mut Core, instr: Instruction) -> Result<(), Exception> { instr.rd(), core.mem .read_word(addr) - .map_err(|e| e.to_exception_load())? as i32 as i64 as DWord, + .map_err(|e| e.to_exception_load())? as i32 as i64 as u64, ); core.advance_pc(); Ok(()) @@ -61,7 +56,7 @@ pub fn lwu(core: &mut Core, instr: Instruction) -> Result<(), Exception> { instr.rd(), core.mem .read_word(addr) - .map_err(|e| e.to_exception_load())? as DWord, + .map_err(|e| e.to_exception_load())? as u64, ); core.advance_pc(); Ok(()) @@ -69,7 +64,7 @@ pub fn lwu(core: &mut Core, instr: Instruction) -> Result<(), Exception> { pub fn sh(core: &mut Core, instr: Instruction) -> Result<(), Exception> { let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s()); - let value = core.reg_read(instr.rs2()) as HWord; + let value = core.reg_read(instr.rs2()) as u16; core.mem .write_hword(addr, value) .map_err(|e| e.to_exception_store())?; @@ -83,7 +78,7 @@ pub fn lh(core: &mut Core, instr: Instruction) -> Result<(), Exception> { instr.rd(), core.mem .read_hword(addr) - .map_err(|e| e.to_exception_load())? as i16 as i64 as DWord, + .map_err(|e| e.to_exception_load())? as i16 as i64 as u64, ); core.advance_pc(); Ok(()) @@ -95,7 +90,7 @@ pub fn lhu(core: &mut Core, instr: Instruction) -> Result<(), Exception> { instr.rd(), core.mem .read_hword(addr) - .map_err(|e| e.to_exception_load())? as DWord, + .map_err(|e| e.to_exception_load())? as u64, ); core.advance_pc(); Ok(()) @@ -103,7 +98,7 @@ pub fn lhu(core: &mut Core, instr: Instruction) -> Result<(), Exception> { pub fn sb(core: &mut Core, instr: Instruction) -> Result<(), Exception> { let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s()); - let value = core.reg_read(instr.rs2()) as Byte; + let value = core.reg_read(instr.rs2()) as u8; core.mem .write_byte(addr, value) .map_err(|e| e.to_exception_store())?; @@ -117,7 +112,7 @@ pub fn lb(core: &mut Core, instr: Instruction) -> Result<(), Exception> { instr.rd(), core.mem .read_byte(addr) - .map_err(|e| e.to_exception_load())? as i8 as i64 as DWord, + .map_err(|e| e.to_exception_load())? as i8 as i64 as u64, ); core.advance_pc(); Ok(()) @@ -129,7 +124,7 @@ pub fn lbu(core: &mut Core, instr: Instruction) -> Result<(), Exception> { instr.rd(), core.mem .read_byte(addr) - .map_err(|e| e.to_exception_load())? as DWord, + .map_err(|e| e.to_exception_load())? as u64, ); core.advance_pc(); Ok(()) |