diff options
Diffstat (limited to 'src/instructions/rvi/mem.rs')
| -rw-r--r-- | src/instructions/rvi/mem.rs | 25 |
1 files changed, 10 insertions, 15 deletions
diff --git a/src/instructions/rvi/mem.rs b/src/instructions/rvi/mem.rs index 071fa79..caa18e1 100644 --- a/src/instructions/rvi/mem.rs +++ b/src/instructions/rvi/mem.rs @@ -4,12 +4,7 @@ // This file is part of TRVE (https://gitea.taitep.se/taitep/trve) // See LICENSE file in the project root for full license text. -use crate::{ - consts::{Byte, DWord, HWord, Word}, - core::Core, - exceptions::Exception, - instructions::Instruction, -}; +use crate::{core::Core, exceptions::Exception, instructions::Instruction}; pub fn sd(core: &mut Core, instr: Instruction) -> Result<(), Exception> { let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s()); @@ -35,7 +30,7 @@ pub fn ld(core: &mut Core, instr: Instruction) -> Result<(), Exception> { pub fn sw(core: &mut Core, instr: Instruction) -> Result<(), Exception> { let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s()); - let value = core.reg_read(instr.rs2()) as Word; + let value = core.reg_read(instr.rs2()) as u32; core.mem .write_word(addr, value) .map_err(|e| e.to_exception_store())?; @@ -49,7 +44,7 @@ pub fn lw(core: &mut Core, instr: Instruction) -> Result<(), Exception> { instr.rd(), core.mem .read_word(addr) - .map_err(|e| e.to_exception_load())? as i32 as i64 as DWord, + .map_err(|e| e.to_exception_load())? as i32 as i64 as u64, ); core.advance_pc(); Ok(()) @@ -61,7 +56,7 @@ pub fn lwu(core: &mut Core, instr: Instruction) -> Result<(), Exception> { instr.rd(), core.mem .read_word(addr) - .map_err(|e| e.to_exception_load())? as DWord, + .map_err(|e| e.to_exception_load())? as u64, ); core.advance_pc(); Ok(()) @@ -69,7 +64,7 @@ pub fn lwu(core: &mut Core, instr: Instruction) -> Result<(), Exception> { pub fn sh(core: &mut Core, instr: Instruction) -> Result<(), Exception> { let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s()); - let value = core.reg_read(instr.rs2()) as HWord; + let value = core.reg_read(instr.rs2()) as u16; core.mem .write_hword(addr, value) .map_err(|e| e.to_exception_store())?; @@ -83,7 +78,7 @@ pub fn lh(core: &mut Core, instr: Instruction) -> Result<(), Exception> { instr.rd(), core.mem .read_hword(addr) - .map_err(|e| e.to_exception_load())? as i16 as i64 as DWord, + .map_err(|e| e.to_exception_load())? as i16 as i64 as u64, ); core.advance_pc(); Ok(()) @@ -95,7 +90,7 @@ pub fn lhu(core: &mut Core, instr: Instruction) -> Result<(), Exception> { instr.rd(), core.mem .read_hword(addr) - .map_err(|e| e.to_exception_load())? as DWord, + .map_err(|e| e.to_exception_load())? as u64, ); core.advance_pc(); Ok(()) @@ -103,7 +98,7 @@ pub fn lhu(core: &mut Core, instr: Instruction) -> Result<(), Exception> { pub fn sb(core: &mut Core, instr: Instruction) -> Result<(), Exception> { let addr = core.reg_read(instr.rs1()).wrapping_add(instr.imm_s()); - let value = core.reg_read(instr.rs2()) as Byte; + let value = core.reg_read(instr.rs2()) as u8; core.mem .write_byte(addr, value) .map_err(|e| e.to_exception_store())?; @@ -117,7 +112,7 @@ pub fn lb(core: &mut Core, instr: Instruction) -> Result<(), Exception> { instr.rd(), core.mem .read_byte(addr) - .map_err(|e| e.to_exception_load())? as i8 as i64 as DWord, + .map_err(|e| e.to_exception_load())? as i8 as i64 as u64, ); core.advance_pc(); Ok(()) @@ -129,7 +124,7 @@ pub fn lbu(core: &mut Core, instr: Instruction) -> Result<(), Exception> { instr.rd(), core.mem .read_byte(addr) - .map_err(|e| e.to_exception_load())? as DWord, + .map_err(|e| e.to_exception_load())? as u64, ); core.advance_pc(); Ok(()) |