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Taitep's RISC-V Emulator
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Age
Commit message (
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Author
2025-12-22
Implement BLTU
taitep
2025-12-22
Implement LH
taitep
2025-12-22
Implement BGEU
taitep
2025-12-22
Pull out memory access instructions from rvi.rs to their own file
taitep
2025-12-22
Implement SW
taitep
2025-12-22
Implement SUB
taitep
2025-12-22
Implement OR
taitep
2025-12-22
Implement AND and improve formatting and ordering in rvi.rs
taitep
2025-12-22
Implement ADD
taitep
2025-12-22
WHY WAS I USING S-TYPE IMMEDIATE IN LD (also add some more debugging info on ...
taitep
2025-12-21
Implement LD and BNE
taitep
2025-12-21
Implement JALR, fix JAL, change how some stuff in instructions.rs is expressed
taitep
2025-12-21
Implement AUIPC
taitep
2025-12-21
Implement ANDI and BEQ
taitep
2025-12-21
Make a dedicated function for advancing the PC by one instruction
taitep
2025-12-21
Implement LB and LBU
taitep
2025-12-21
Implement SB
taitep
2025-12-21
Fix sd address calculation
taitep
2025-12-21
Remove a debug print from SLLI
taitep
2025-12-21
Implement SLLI and fix sign extension of immediates for I-type and S-type ins...
taitep
2025-12-21
Add JAL and change some of the formatting on previous instructions to be cleaner
taitep
2025-12-21
(BIG CHANGE) Switch instruction identification/execution to use a plain match...
taitep
2025-12-01
Add license/copyright notices to top of each source file (where applicable)
taitep
2025-10-21
Add support for addiw and lui
taitep
2025-10-14
Add a todo
taitep
2025-10-14
Move funct3 values to rvi.rs instead of being in opcodes.rs
taitep
2025-10-10
some debugging stuff and SECOND OPCODE!
taitep
2025-10-07
FIRST INSTRUCTION WORKING
taitep