summaryrefslogtreecommitdiff
path: root/src/mem.rs
AgeCommit message (Collapse)Author
2026-01-09Remove RamVersionClaim::reset as ive figured out it wont be neededtaitep
2026-01-06Implement the memory version system that will be necessary for LR/SCtaitep
2026-01-02remove get_atomic_(d)word because its not used yet and the idea for how ↵taitep
atomics will be done will have to be reworked
2025-12-31Make MMIO devices not have control of the address of exceptionstaitep
2025-12-30Improve exception dumps and general debug info, make the emulator capable of ↵taitep
running the riscv ISA tests, and perform some general fixes i found while making it pass the tests for RV64I
2025-12-28Remove consts.rs and just use plain typestaitep
2025-12-27Add exception values (what will go in mtval/stval)taitep
2025-12-27Add checks to make sure that ram has a size that is a multiple of 8taitep
2025-12-27Relicense to BSD 2-Clause to align better with the RISC-V communitytaitep
2025-12-26(BIG CHANGE) memory handling has changed, MMIO is now a 2 level page table, ↵taitep
misaligned access supported, addresses not internally split to page and offset immediately, all load/store instructions implemented. Might still have bugs
2025-12-24Add a default implementation for the memory device interface that just ↵taitep
returns access faults
2025-12-24EXCEPTION SYSTEM (initial version - may change later)taitep
2025-12-01Add license/copyright notices to top of each source file (where applicable)taitep
2025-10-09Make fields of DeviceEntry publictaitep
2025-10-09Make some constants and type aliases publictaitep
2025-10-07Make fields of MemConfig public to allow creating onetaitep
2025-09-28Allow identification of the type of memory (ram or mmio) backing a specific pagetaitep
2025-09-27actually no NOW the memory interface is "done"taitep
2025-09-27Initial stuff and memory implementationtaitep
generated by cgit v1.2.3 (git 2.46.0) at 2026-03-31 06:03:29 +0000