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AgeCommit message (Expand)Author
2025-12-21Allow other image file names through cli args, increase ram size, update readmetaitep
2025-12-21Implement ANDI and BEQtaitep
2025-12-21Remove unused imports from the UART implementationtaitep
2025-12-21Make a dedicated function for advancing the PC by one instructiontaitep
2025-12-21Implement LB and LBUtaitep
2025-12-21Make the UART not constantly flush outputtaitep
2025-12-21Add a basic UART (very much temporary, its performance is most likely horribletaitep
2025-12-21Implement SBtaitep
2025-12-21Fix sd address calculationtaitep
2025-12-21Remove a debug print from SLLItaitep
2025-12-21Implement SLLI and fix sign extension of immediates for I-type and S-type ins...taitep
2025-12-21Get rid of some useless warnings in main.rstaitep
2025-12-21Add decode functions for immediate shifts (funct6 and imm_shamt), make decode...taitep
2025-12-21Add JAL and change some of the formatting on previous instructions to be cleanertaitep
2025-12-21(BIG CHANGE) Switch instruction identification/execution to use a plain match...taitep
2025-12-01Add license/copyright notices to top of each source file (where applicable)taitep
2025-11-18rename to TRVEtaitep
2025-10-21Add support for addiw and luitaitep
2025-10-14Add a todotaitep
2025-10-14Move funct3 values to rvi.rs instead of being in opcodes.rstaitep
2025-10-10some debugging stuff and SECOND OPCODE!taitep
2025-10-09Make fields of DeviceEntry publictaitep
2025-10-09Make some constants and type aliases publictaitep
2025-10-07FIRST INSTRUCTION WORKINGtaitep
2025-10-07Make sure unsupported/illegal instructions are caughttaitep
2025-10-07Make fields and register access functions of Core accessible to the rest of t...taitep
2025-10-07Make fields of MemConfig public to allow creating onetaitep
2025-10-04I guess its a working execution loop?taitep
2025-10-03Swap out execution status for instructions returning an InstructionResulttaitep
2025-09-30Initial instruction execution code i guesstaitep
2025-09-28Allow identification of the type of memory (ram or mmio) backing a specific pagetaitep
2025-09-27base core state & instruction decodertaitep
2025-09-27actually no NOW the memory interface is "done"taitep
2025-09-27Initial stuff and memory implementationtaitep
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