trve.git - Taitep's RISC-V Emulator

Age	Commit message (Expand)	Author
2026-03-05	update git repo linksHEAD main	taitep
2026-01-13	Implement Zalrsc	taitep
2026-01-09	Remove RamVersionClaim::reset as ive figured out it wont be needed	taitep
2026-01-06	Implement the memory version system that will be necessary for LR/SC	taitep
2026-01-02	remove get_atomic_(d)word because its not used yet and the idea for how atomi...	taitep
2025-12-31	Make MMIO devices not have control of the address of exceptions	taitep
2025-12-30	Improve exception dumps and general debug info, make the emulator capable of ...	taitep
2025-12-28	Remove consts.rs and just use plain types	taitep
2025-12-27	Add exception values (what will go in mtval/stval)	taitep
2025-12-27	Add checks to make sure that ram has a size that is a multiple of 8	taitep
2025-12-27	Relicense to BSD 2-Clause to align better with the RISC-V community	taitep
2025-12-26	(BIG CHANGE) memory handling has changed, MMIO is now a 2 level page table, m...	taitep
2025-12-24	Add a default implementation for the memory device interface that just return...	taitep
2025-12-24	EXCEPTION SYSTEM (initial version - may change later)	taitep
2025-12-01	Add license/copyright notices to top of each source file (where applicable)	taitep
2025-10-09	Make fields of DeviceEntry public	taitep
2025-10-09	Make some constants and type aliases public	taitep
2025-10-07	Make fields of MemConfig public to allow creating one	taitep
2025-09-28	Allow identification of the type of memory (ram or mmio) backing a specific page	taitep
2025-09-27	actually no NOW the memory interface is "done"	taitep
2025-09-27	Initial stuff and memory implementation	taitep