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path: root/src/basic_uart.rs
AgeCommit message (Collapse)Author
2026-01-29Replace custom UART with a sifive uart subsettaitep
2025-12-31Make MMIO devices not have control of the address of exceptionstaitep
2025-12-28Remove consts.rs and just use plain typestaitep
2025-12-27Add exception values (what will go in mtval/stval)taitep
2025-12-27Relicense to BSD 2-Clause to align better with the RISC-V communitytaitep
2025-12-26(BIG CHANGE) memory handling has changed, MMIO is now a 2 level page table, ↵taitep
misaligned access supported, addresses not internally split to page and offset immediately, all load/store instructions implemented. Might still have bugs
2025-12-24EXCEPTION SYSTEM (initial version - may change later)taitep
2025-12-23Add license headers to files missing themtaitep
2025-12-21Improve UART by using nonblocking stdintaitep
2025-12-21Remove unused imports from the UART implementationtaitep
2025-12-21Make the UART not constantly flush outputtaitep
2025-12-21Add a basic UART (very much temporary, its performance is most likely horribletaitep
generated by cgit v1.2.3 (git 2.46.0) at 2026-03-31 04:22:38 +0000